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138 lines
3.9 KiB
138 lines
3.9 KiB
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IMX_USDHC_H
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#define IMX_USDHC_H
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#include <drivers/mmc.h>
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typedef struct imx_usdhc_params {
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uintptr_t reg_base;
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int clk_rate;
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int bus_width;
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unsigned int flags;
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} imx_usdhc_params_t;
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void imx_usdhc_init(imx_usdhc_params_t *params,
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struct mmc_device_info *mmc_dev_info);
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/* iMX MMC registers definition */
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#define DSADDR 0x000
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#define BLKATT 0x004
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#define CMDARG 0x008
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#define CMDRSP0 0x010
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#define CMDRSP1 0x014
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#define CMDRSP2 0x018
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#define CMDRSP3 0x01c
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#define XFERTYPE 0x00c
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#define XFERTYPE_CMD(x) (((x) & 0x3f) << 24)
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#define XFERTYPE_CMDTYP_ABORT (3 << 22)
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#define XFERTYPE_DPSEL BIT(21)
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#define XFERTYPE_CICEN BIT(20)
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#define XFERTYPE_CCCEN BIT(19)
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#define XFERTYPE_RSPTYP_136 BIT(16)
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#define XFERTYPE_RSPTYP_48 BIT(17)
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#define XFERTYPE_RSPTYP_48_BUSY (BIT(16) | BIT(17))
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#define PSTATE 0x024
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#define PSTATE_DAT0 BIT(24)
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#define PSTATE_DLA BIT(2)
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#define PSTATE_CDIHB BIT(1)
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#define PSTATE_CIHB BIT(0)
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#define PROTCTRL 0x028
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#define PROTCTRL_LE BIT(5)
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#define PROTCTRL_WIDTH_4 BIT(1)
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#define PROTCTRL_WIDTH_8 BIT(2)
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#define PROTCTRL_WIDTH_MASK 0x6
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#define SYSCTRL 0x02c
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#define SYSCTRL_RSTD BIT(26)
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#define SYSCTRL_RSTC BIT(25)
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#define SYSCTRL_RSTA BIT(24)
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#define SYSCTRL_CLOCK_MASK 0x0000fff0
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#define SYSCTRL_TIMEOUT_MASK 0x000f0000
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#define SYSCTRL_TIMEOUT(x) ((0xf & (x)) << 16)
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#define INTSTAT 0x030
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#define INTSTAT_DMAE BIT(28)
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#define INTSTAT_DEBE BIT(22)
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#define INTSTAT_DCE BIT(21)
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#define INTSTAT_DTOE BIT(20)
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#define INTSTAT_CIE BIT(19)
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#define INTSTAT_CEBE BIT(18)
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#define INTSTAT_CCE BIT(17)
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#define INTSTAT_DINT BIT(3)
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#define INTSTAT_BGE BIT(2)
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#define INTSTAT_TC BIT(1)
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#define INTSTAT_CC BIT(0)
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#define CMD_ERR (INTSTAT_CIE | INTSTAT_CEBE | INTSTAT_CCE)
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#define DATA_ERR (INTSTAT_DMAE | INTSTAT_DEBE | INTSTAT_DCE | \
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INTSTAT_DTOE)
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#define DATA_COMPLETE (INTSTAT_DINT | INTSTAT_TC)
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#define INTSTATEN 0x034
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#define INTSTATEN_DEBE BIT(22)
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#define INTSTATEN_DCE BIT(21)
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#define INTSTATEN_DTOE BIT(20)
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#define INTSTATEN_CIE BIT(19)
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#define INTSTATEN_CEBE BIT(18)
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#define INTSTATEN_CCE BIT(17)
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#define INTSTATEN_CTOE BIT(16)
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#define INTSTATEN_CINT BIT(8)
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#define INTSTATEN_BRR BIT(5)
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#define INTSTATEN_BWR BIT(4)
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#define INTSTATEN_DINT BIT(3)
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#define INTSTATEN_TC BIT(1)
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#define INTSTATEN_CC BIT(0)
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#define EMMC_INTSTATEN_BITS (INTSTATEN_CC | INTSTATEN_TC | INTSTATEN_DINT | \
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INTSTATEN_BWR | INTSTATEN_BRR | INTSTATEN_CINT | \
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INTSTATEN_CTOE | INTSTATEN_CCE | INTSTATEN_CEBE | \
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INTSTATEN_CIE | INTSTATEN_DTOE | INTSTATEN_DCE | \
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INTSTATEN_DEBE)
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#define INTSIGEN 0x038
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#define WATERMARKLEV 0x044
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#define WMKLV_RD_MASK 0xff
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#define WMKLV_WR_MASK 0x00ff0000
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#define WMKLV_MASK (WMKLV_RD_MASK | WMKLV_WR_MASK)
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#define MIXCTRL 0x048
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#define MIXCTRL_MSBSEL BIT(5)
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#define MIXCTRL_DTDSEL BIT(4)
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#define MIXCTRL_DDREN BIT(3)
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#define MIXCTRL_AC12EN BIT(2)
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#define MIXCTRL_BCEN BIT(1)
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#define MIXCTRL_DMAEN BIT(0)
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#define MIXCTRL_DATMASK 0x7f
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#define DLLCTRL 0x060
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#define CLKTUNECTRLSTS 0x068
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#define VENDSPEC 0x0c0
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#define VENDSPEC_RSRV1 BIT(29)
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#define VENDSPEC_CARD_CLKEN BIT(14)
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#define VENDSPEC_PER_CLKEN BIT(13)
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#define VENDSPEC_AHB_CLKEN BIT(12)
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#define VENDSPEC_IPG_CLKEN BIT(11)
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#define VENDSPEC_AC12_CHKBUSY BIT(3)
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#define VENDSPEC_EXTDMA BIT(0)
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#define VENDSPEC_INIT (VENDSPEC_RSRV1 | VENDSPEC_CARD_CLKEN | \
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VENDSPEC_PER_CLKEN | VENDSPEC_AHB_CLKEN | \
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VENDSPEC_IPG_CLKEN | VENDSPEC_AC12_CHKBUSY | \
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VENDSPEC_EXTDMA)
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#define MMCBOOT 0x0c4
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#define mmio_clrsetbits32(addr, clear, set) mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
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#define mmio_clrbits32(addr, clear) mmio_write_32(addr, mmio_read_32(addr) & ~(clear))
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#define mmio_setbits32(addr, set) mmio_write_32(addr, mmio_read_32(addr) | (set))
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#endif /* IMX_USDHC_H */
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