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619 lines
19 KiB
619 lines
19 KiB
/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARCH_HELPERS_H
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#define ARCH_HELPERS_H
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#include <cdefs.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include <arch.h>
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/**********************************************************************
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* Macros which create inline functions to read or write CPU system
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* registers
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*********************************************************************/
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#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
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static inline u_register_t read_ ## _name(void) \
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{ \
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u_register_t v; \
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__asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
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return v; \
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}
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#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
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static inline void write_ ## _name(u_register_t v) \
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{ \
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__asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
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}
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#define SYSREG_WRITE_CONST(reg_name, v) \
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__asm__ volatile ("msr " #reg_name ", %0" : : "i" (v))
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/* Define read function for system register */
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#define DEFINE_SYSREG_READ_FUNC(_name) \
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_DEFINE_SYSREG_READ_FUNC(_name, _name)
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/* Define read & write function for system register */
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#define DEFINE_SYSREG_RW_FUNCS(_name) \
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_DEFINE_SYSREG_READ_FUNC(_name, _name) \
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_DEFINE_SYSREG_WRITE_FUNC(_name, _name)
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/* Define read & write function for renamed system register */
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#define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
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_DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
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_DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
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/* Define read function for renamed system register */
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#define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \
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_DEFINE_SYSREG_READ_FUNC(_name, _reg_name)
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/* Define write function for renamed system register */
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#define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
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_DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
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/**********************************************************************
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* Macros to create inline functions for system instructions
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*********************************************************************/
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/* Define function for simple system instruction */
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#define DEFINE_SYSOP_FUNC(_op) \
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static inline void _op(void) \
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{ \
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__asm__ (#_op); \
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}
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/* Define function for system instruction with register parameter */
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#define DEFINE_SYSOP_PARAM_FUNC(_op) \
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static inline void _op(uint64_t v) \
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{ \
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__asm__ (#_op " %0" : : "r" (v)); \
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}
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/* Define function for system instruction with type specifier */
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#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
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static inline void _op ## _type(void) \
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{ \
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__asm__ (#_op " " #_type : : : "memory"); \
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}
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/* Define function for system instruction with register parameter */
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#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
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static inline void _op ## _type(uint64_t v) \
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{ \
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__asm__ (#_op " " #_type ", %0" : : "r" (v)); \
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}
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/*******************************************************************************
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* TLB maintenance accessor prototypes
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******************************************************************************/
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#if ERRATA_A57_813419 || ERRATA_A76_1286807
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/*
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* Define function for TLBI instruction with type specifier that implements
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* the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
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* Cortex-A76.
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*/
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#define DEFINE_TLBIOP_ERRATA_TYPE_FUNC(_type)\
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static inline void tlbi ## _type(void) \
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{ \
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__asm__("tlbi " #_type "\n" \
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"dsb ish\n" \
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"tlbi " #_type); \
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}
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/*
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* Define function for TLBI instruction with register parameter that implements
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* the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
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* Cortex-A76.
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*/
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#define DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(_type) \
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static inline void tlbi ## _type(uint64_t v) \
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{ \
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__asm__("tlbi " #_type ", %0\n" \
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"dsb ish\n" \
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"tlbi " #_type ", %0" : : "r" (v)); \
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}
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#endif /* ERRATA_A57_813419 */
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#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
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/*
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* Define function for DC instruction with register parameter that enables
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* the workaround for errata 819472, 824069 and 827319 of Cortex-A53.
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*/
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#define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \
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static inline void dc ## _name(uint64_t v) \
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{ \
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__asm__("dc " #_type ", %0" : : "r" (v)); \
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}
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#endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */
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#if ERRATA_A57_813419
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
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#elif ERRATA_A76_1286807
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1)
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1is)
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2)
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2is)
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
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DEFINE_TLBIOP_ERRATA_TYPE_FUNC(vmalle1)
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#else
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
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DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
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#endif
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#if ERRATA_A57_813419
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
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#elif ERRATA_A76_1286807
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaae1is)
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaale1is)
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae2is)
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale2is)
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
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DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
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#else
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
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#endif
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/*******************************************************************************
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* Cache maintenance accessor prototypes
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******************************************************************************/
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
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#if ERRATA_A53_827319
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DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw)
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#else
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
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#endif
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#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
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DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac)
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#else
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
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#endif
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
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#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
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DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac)
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#else
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
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#endif
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DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
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/*******************************************************************************
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* Address translation accessor prototypes
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******************************************************************************/
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DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r)
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DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r)
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/*******************************************************************************
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* Strip Pointer Authentication Code
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******************************************************************************/
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DEFINE_SYSOP_PARAM_FUNC(xpaci)
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void flush_dcache_range(uintptr_t addr, size_t size);
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void clean_dcache_range(uintptr_t addr, size_t size);
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void inv_dcache_range(uintptr_t addr, size_t size);
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bool is_dcache_enabled(void);
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void dcsw_op_louis(u_register_t op_type);
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void dcsw_op_all(u_register_t op_type);
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void disable_mmu_el1(void);
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void disable_mmu_el3(void);
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void disable_mmu_icache_el1(void);
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void disable_mmu_icache_el3(void);
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/*******************************************************************************
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* Misc. accessor prototypes
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******************************************************************************/
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#define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val)
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#define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
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DEFINE_SYSREG_RW_FUNCS(par_el1)
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DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64isar0_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
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DEFINE_SYSREG_READ_FUNC(id_afr0_el1)
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DEFINE_SYSREG_READ_FUNC(CurrentEl)
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DEFINE_SYSREG_READ_FUNC(ctr_el0)
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DEFINE_SYSREG_RW_FUNCS(daif)
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DEFINE_SYSREG_RW_FUNCS(spsr_el1)
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DEFINE_SYSREG_RW_FUNCS(spsr_el2)
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DEFINE_SYSREG_RW_FUNCS(spsr_el3)
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DEFINE_SYSREG_RW_FUNCS(elr_el1)
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DEFINE_SYSREG_RW_FUNCS(elr_el2)
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DEFINE_SYSREG_RW_FUNCS(elr_el3)
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DEFINE_SYSOP_FUNC(wfi)
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DEFINE_SYSOP_FUNC(wfe)
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DEFINE_SYSOP_FUNC(sev)
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DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
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DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
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DEFINE_SYSOP_TYPE_FUNC(dmb, st)
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DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
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DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
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DEFINE_SYSOP_TYPE_FUNC(dsb, nsh)
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DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
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DEFINE_SYSOP_TYPE_FUNC(dmb, oshld)
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DEFINE_SYSOP_TYPE_FUNC(dmb, oshst)
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DEFINE_SYSOP_TYPE_FUNC(dmb, osh)
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DEFINE_SYSOP_TYPE_FUNC(dmb, nshld)
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DEFINE_SYSOP_TYPE_FUNC(dmb, nshst)
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DEFINE_SYSOP_TYPE_FUNC(dmb, nsh)
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DEFINE_SYSOP_TYPE_FUNC(dmb, ishld)
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DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
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DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
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DEFINE_SYSOP_FUNC(isb)
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static inline void enable_irq(void)
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{
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/*
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* The compiler memory barrier will prevent the compiler from
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* scheduling non-volatile memory access after the write to the
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* register.
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*
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* This could happen if some initialization code issues non-volatile
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* accesses to an area used by an interrupt handler, in the assumption
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* that it is safe as the interrupts are disabled at the time it does
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* that (according to program order). However, non-volatile accesses
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* are not necessarily in program order relatively with volatile inline
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* assembly statements (and volatile accesses).
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*/
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COMPILER_BARRIER();
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write_daifclr(DAIF_IRQ_BIT);
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isb();
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}
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static inline void enable_fiq(void)
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{
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COMPILER_BARRIER();
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write_daifclr(DAIF_FIQ_BIT);
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isb();
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}
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static inline void enable_serror(void)
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{
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COMPILER_BARRIER();
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write_daifclr(DAIF_ABT_BIT);
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isb();
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}
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static inline void enable_debug_exceptions(void)
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{
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COMPILER_BARRIER();
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write_daifclr(DAIF_DBG_BIT);
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isb();
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}
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static inline void disable_irq(void)
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{
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COMPILER_BARRIER();
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write_daifset(DAIF_IRQ_BIT);
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isb();
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}
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static inline void disable_fiq(void)
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{
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COMPILER_BARRIER();
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write_daifset(DAIF_FIQ_BIT);
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isb();
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}
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static inline void disable_serror(void)
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{
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COMPILER_BARRIER();
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write_daifset(DAIF_ABT_BIT);
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isb();
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}
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static inline void disable_debug_exceptions(void)
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{
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COMPILER_BARRIER();
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write_daifset(DAIF_DBG_BIT);
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isb();
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}
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void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
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uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
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/*******************************************************************************
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* System register accessor prototypes
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******************************************************************************/
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DEFINE_SYSREG_READ_FUNC(midr_el1)
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DEFINE_SYSREG_READ_FUNC(mpidr_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64mmfr1_el1)
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DEFINE_SYSREG_RW_FUNCS(scr_el3)
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DEFINE_SYSREG_RW_FUNCS(hcr_el2)
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DEFINE_SYSREG_RW_FUNCS(vbar_el1)
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DEFINE_SYSREG_RW_FUNCS(vbar_el2)
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DEFINE_SYSREG_RW_FUNCS(vbar_el3)
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DEFINE_SYSREG_RW_FUNCS(sctlr_el1)
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DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
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DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
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DEFINE_SYSREG_RW_FUNCS(actlr_el1)
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DEFINE_SYSREG_RW_FUNCS(actlr_el2)
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DEFINE_SYSREG_RW_FUNCS(actlr_el3)
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DEFINE_SYSREG_RW_FUNCS(esr_el1)
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DEFINE_SYSREG_RW_FUNCS(esr_el2)
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DEFINE_SYSREG_RW_FUNCS(esr_el3)
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DEFINE_SYSREG_RW_FUNCS(afsr0_el1)
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DEFINE_SYSREG_RW_FUNCS(afsr0_el2)
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DEFINE_SYSREG_RW_FUNCS(afsr0_el3)
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DEFINE_SYSREG_RW_FUNCS(afsr1_el1)
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DEFINE_SYSREG_RW_FUNCS(afsr1_el2)
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DEFINE_SYSREG_RW_FUNCS(afsr1_el3)
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DEFINE_SYSREG_RW_FUNCS(far_el1)
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DEFINE_SYSREG_RW_FUNCS(far_el2)
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DEFINE_SYSREG_RW_FUNCS(far_el3)
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DEFINE_SYSREG_RW_FUNCS(mair_el1)
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DEFINE_SYSREG_RW_FUNCS(mair_el2)
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DEFINE_SYSREG_RW_FUNCS(mair_el3)
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DEFINE_SYSREG_RW_FUNCS(amair_el1)
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DEFINE_SYSREG_RW_FUNCS(amair_el2)
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DEFINE_SYSREG_RW_FUNCS(amair_el3)
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DEFINE_SYSREG_READ_FUNC(rvbar_el1)
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DEFINE_SYSREG_READ_FUNC(rvbar_el2)
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DEFINE_SYSREG_READ_FUNC(rvbar_el3)
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DEFINE_SYSREG_RW_FUNCS(rmr_el1)
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DEFINE_SYSREG_RW_FUNCS(rmr_el2)
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DEFINE_SYSREG_RW_FUNCS(rmr_el3)
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DEFINE_SYSREG_RW_FUNCS(tcr_el1)
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DEFINE_SYSREG_RW_FUNCS(tcr_el2)
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DEFINE_SYSREG_RW_FUNCS(tcr_el3)
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DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
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DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
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DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
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DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
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DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
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DEFINE_SYSREG_RW_FUNCS(cptr_el2)
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DEFINE_SYSREG_RW_FUNCS(cptr_el3)
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DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
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DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
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DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
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DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2)
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DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2)
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DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
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DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
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DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
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DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0)
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DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0)
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DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0)
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DEFINE_SYSREG_READ_FUNC(cntpct_el0)
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DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
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#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
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CNTP_CTL_ENABLE_MASK)
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#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
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CNTP_CTL_IMASK_MASK)
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#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
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CNTP_CTL_ISTATUS_MASK)
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#define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
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#define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
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#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
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#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
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DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
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DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
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DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
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DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
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DEFINE_SYSREG_READ_FUNC(isr_el1)
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DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
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DEFINE_SYSREG_RW_FUNCS(mdcr_el3)
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DEFINE_SYSREG_RW_FUNCS(hstr_el2)
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DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
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/* GICv3 System Registers */
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DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
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DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
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DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
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DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3)
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DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1)
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DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1)
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DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1)
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DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1)
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DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
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DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
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DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
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DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R)
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DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0)
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DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0)
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DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0)
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DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0)
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DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
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DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
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DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3)
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DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2)
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DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2)
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DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
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DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
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DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)
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DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1)
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DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1)
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DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1)
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|
DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1)
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DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
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DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
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/* Armv8.2 Registers */
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DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
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|
|
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/* Armv8.3 Pointer Authentication Registers */
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DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1)
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|
|
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/* Armv8.5 MTE Registers */
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DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
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|
DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
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|
|
|
/* Armv8.5 FEAT_RNG Registers */
|
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DEFINE_SYSREG_READ_FUNC(rndr)
|
|
DEFINE_SYSREG_READ_FUNC(rndrrs)
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|
|
|
/* DynamIQ Shared Unit power management */
|
|
DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
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|
|
|
#define IS_IN_EL(x) \
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|
(GET_EL(read_CurrentEl()) == MODE_EL##x)
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|
|
|
#define IS_IN_EL1() IS_IN_EL(1)
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|
#define IS_IN_EL2() IS_IN_EL(2)
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|
#define IS_IN_EL3() IS_IN_EL(3)
|
|
|
|
static inline unsigned int get_current_el(void)
|
|
{
|
|
return GET_EL(read_CurrentEl());
|
|
}
|
|
|
|
static inline unsigned int get_current_el_maybe_constant(void)
|
|
{
|
|
#if defined(IMAGE_AT_EL1)
|
|
return 1;
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|
#elif defined(IMAGE_AT_EL2)
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|
return 2; /* no use-case in TF-A */
|
|
#elif defined(IMAGE_AT_EL3)
|
|
return 3;
|
|
#else
|
|
/*
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|
* If we do not know which exception level this is being built for
|
|
* (e.g. built for library), fall back to run-time detection.
|
|
*/
|
|
return get_current_el();
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|
#endif
|
|
}
|
|
|
|
/*
|
|
* Check if an EL is implemented from AA64PFR0 register fields.
|
|
*/
|
|
static inline uint64_t el_implemented(unsigned int el)
|
|
{
|
|
if (el > 3U) {
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|
return EL_IMPL_NONE;
|
|
} else {
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|
unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el;
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|
|
|
return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK;
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|
}
|
|
}
|
|
|
|
/* Previously defined accesor functions with incomplete register names */
|
|
|
|
#define read_current_el() read_CurrentEl()
|
|
|
|
#define dsb() dsbsy()
|
|
|
|
#define read_midr() read_midr_el1()
|
|
|
|
#define read_mpidr() read_mpidr_el1()
|
|
|
|
#define read_scr() read_scr_el3()
|
|
#define write_scr(_v) write_scr_el3(_v)
|
|
|
|
#define read_hcr() read_hcr_el2()
|
|
#define write_hcr(_v) write_hcr_el2(_v)
|
|
|
|
#define read_cpacr() read_cpacr_el1()
|
|
#define write_cpacr(_v) write_cpacr_el1(_v)
|
|
|
|
#define read_clusterpwrdn() read_clusterpwrdn_el1()
|
|
#define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v)
|
|
|
|
#if ERRATA_SPECULATIVE_AT
|
|
/*
|
|
* Assuming SCTLR.M bit is already enabled
|
|
* 1. Enable page table walk by clearing TCR_EL1.EPDx bits
|
|
* 2. Execute AT instruction for lower EL1/0
|
|
* 3. Disable page table walk by setting TCR_EL1.EPDx bits
|
|
*/
|
|
#define AT(_at_inst, _va) \
|
|
{ \
|
|
assert((read_sctlr_el1() & SCTLR_M_BIT) != 0ULL); \
|
|
write_tcr_el1(read_tcr_el1() & ~(TCR_EPD0_BIT | TCR_EPD1_BIT)); \
|
|
isb(); \
|
|
_at_inst(_va); \
|
|
write_tcr_el1(read_tcr_el1() | (TCR_EPD0_BIT | TCR_EPD1_BIT)); \
|
|
isb(); \
|
|
}
|
|
#else
|
|
#define AT(_at_inst, _va) _at_inst(_va);
|
|
#endif
|
|
|
|
#endif /* ARCH_HELPERS_H */
|