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189 lines
6.4 KiB
189 lines
6.4 KiB
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef GICV2_H
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#define GICV2_H
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#include <drivers/arm/gic_common.h>
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/*******************************************************************************
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* GICv2 miscellaneous definitions
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******************************************************************************/
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/* Interrupt group definitions */
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#define GICV2_INTR_GROUP0 U(0)
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#define GICV2_INTR_GROUP1 U(1)
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/* Interrupt IDs reported by the HPPIR and IAR registers */
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#define PENDING_G1_INTID U(1022)
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/* GICv2 can only target up to 8 PEs */
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#define GICV2_MAX_TARGET_PE U(8)
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/*******************************************************************************
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* GICv2 specific Distributor interface register offsets and constants.
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******************************************************************************/
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#define GICD_ITARGETSR U(0x800)
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#define GICD_SGIR U(0xF00)
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#define GICD_CPENDSGIR U(0xF10)
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#define GICD_SPENDSGIR U(0xF20)
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#define GICD_PIDR2_GICV2 U(0xFE8)
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#define ITARGETSR_SHIFT 2
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#define GIC_TARGET_CPU_MASK U(0xff)
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#define CPENDSGIR_SHIFT 2
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#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT
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#define SGIR_TGTLSTFLT_SHIFT 24
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#define SGIR_TGTLSTFLT_MASK U(0x3)
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#define SGIR_TGTLST_SHIFT 16
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#define SGIR_TGTLST_MASK U(0xff)
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#define SGIR_INTID_MASK ULL(0xf)
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#define SGIR_TGT_SPECIFIC U(0)
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#define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, intid) \
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((((tgt_lst_flt) & SGIR_TGTLSTFLT_MASK) << SGIR_TGTLSTFLT_SHIFT) | \
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(((tgt) & SGIR_TGTLST_MASK) << SGIR_TGTLST_SHIFT) | \
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((intid) & SGIR_INTID_MASK))
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/*******************************************************************************
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* GICv2 specific CPU interface register offsets and constants.
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******************************************************************************/
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/* Physical CPU Interface registers */
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#define GICC_CTLR U(0x0)
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#define GICC_PMR U(0x4)
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#define GICC_BPR U(0x8)
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#define GICC_IAR U(0xC)
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#define GICC_EOIR U(0x10)
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#define GICC_RPR U(0x14)
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#define GICC_HPPIR U(0x18)
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#define GICC_AHPPIR U(0x28)
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#define GICC_IIDR U(0xFC)
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#define GICC_DIR U(0x1000)
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#define GICC_PRIODROP GICC_EOIR
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/* GICC_CTLR bit definitions */
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#define EOI_MODE_NS BIT_32(10)
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#define EOI_MODE_S BIT_32(9)
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#define IRQ_BYP_DIS_GRP1 BIT_32(8)
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#define FIQ_BYP_DIS_GRP1 BIT_32(7)
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#define IRQ_BYP_DIS_GRP0 BIT_32(6)
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#define FIQ_BYP_DIS_GRP0 BIT_32(5)
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#define CBPR BIT_32(4)
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#define FIQ_EN_SHIFT 3
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#define FIQ_EN_BIT BIT_32(FIQ_EN_SHIFT)
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#define ACK_CTL BIT_32(2)
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/* GICC_IIDR bit masks and shifts */
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#define GICC_IIDR_PID_SHIFT 20
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#define GICC_IIDR_ARCH_SHIFT 16
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#define GICC_IIDR_REV_SHIFT 12
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#define GICC_IIDR_IMP_SHIFT 0
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#define GICC_IIDR_PID_MASK U(0xfff)
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#define GICC_IIDR_ARCH_MASK U(0xf)
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#define GICC_IIDR_REV_MASK U(0xf)
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#define GICC_IIDR_IMP_MASK U(0xfff)
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/* HYP view virtual CPU Interface registers */
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#define GICH_CTL U(0x0)
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#define GICH_VTR U(0x4)
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#define GICH_ELRSR0 U(0x30)
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#define GICH_ELRSR1 U(0x34)
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#define GICH_APR0 U(0xF0)
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#define GICH_LR_BASE U(0x100)
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/* Virtual CPU Interface registers */
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#define GICV_CTL U(0x0)
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#define GICV_PRIMASK U(0x4)
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#define GICV_BP U(0x8)
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#define GICV_INTACK U(0xC)
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#define GICV_EOI U(0x10)
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#define GICV_RUNNINGPRI U(0x14)
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#define GICV_HIGHESTPEND U(0x18)
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#define GICV_DEACTIVATE U(0x1000)
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/* GICD_CTLR bit definitions */
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#define CTLR_ENABLE_G1_SHIFT 1
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#define CTLR_ENABLE_G1_MASK U(0x1)
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#define CTLR_ENABLE_G1_BIT BIT_32(CTLR_ENABLE_G1_SHIFT)
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/* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
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#define INT_ID_MASK U(0x3ff)
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#ifndef __ASSEMBLER__
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#include <cdefs.h>
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#include <stdint.h>
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#include <common/interrupt_props.h>
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/*******************************************************************************
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* This structure describes some of the implementation defined attributes of
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* the GICv2 IP. It is used by the platform port to specify these attributes
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* in order to initialize the GICv2 driver. The attributes are described
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* below.
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*
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* The 'gicd_base' field contains the base address of the Distributor interface
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* programmer's view.
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*
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* The 'gicc_base' field contains the base address of the CPU Interface
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* programmer's view.
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*
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* The 'target_masks' is a pointer to an array containing 'target_masks_num'
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* elements. The GIC driver will populate the array with per-PE target mask to
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* use to when targeting interrupts.
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*
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* The 'interrupt_props' field is a pointer to an array that enumerates secure
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* interrupts and their properties. If this field is not NULL, both
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* 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored.
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*
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* The 'interrupt_props_num' field contains the number of entries in the
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* 'interrupt_props' array. If this field is non-zero, 'g0_interrupt_num' is
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* ignored.
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******************************************************************************/
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typedef struct gicv2_driver_data {
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uintptr_t gicd_base;
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uintptr_t gicc_base;
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unsigned int *target_masks;
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unsigned int target_masks_num;
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const interrupt_prop_t *interrupt_props;
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unsigned int interrupt_props_num;
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} gicv2_driver_data_t;
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/*******************************************************************************
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* Function prototypes
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******************************************************************************/
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void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data);
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void gicv2_distif_init(void);
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void gicv2_pcpu_distif_init(void);
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void gicv2_cpuif_enable(void);
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void gicv2_cpuif_disable(void);
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unsigned int gicv2_is_fiq_enabled(void);
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unsigned int gicv2_get_pending_interrupt_type(void);
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unsigned int gicv2_get_pending_interrupt_id(void);
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unsigned int gicv2_acknowledge_interrupt(void);
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void gicv2_end_of_interrupt(unsigned int id);
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unsigned int gicv2_get_interrupt_group(unsigned int id);
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unsigned int gicv2_get_running_priority(void);
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void gicv2_set_pe_target_mask(unsigned int proc_num);
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unsigned int gicv2_get_interrupt_active(unsigned int id);
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void gicv2_enable_interrupt(unsigned int id);
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void gicv2_disable_interrupt(unsigned int id);
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void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority);
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void gicv2_set_interrupt_type(unsigned int id, unsigned int type);
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void gicv2_raise_sgi(int sgi_num, int proc_num);
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void gicv2_set_spi_routing(unsigned int id, int proc_num);
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void gicv2_set_interrupt_pending(unsigned int id);
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void gicv2_clear_interrupt_pending(unsigned int id);
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unsigned int gicv2_set_pmr(unsigned int mask);
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void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg);
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#endif /* __ASSEMBLER__ */
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#endif /* GICV2_H */
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