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105 lines
3.4 KiB
105 lines
3.4 KiB
/*
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TZC_DMC620_H
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#define TZC_DMC620_H
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#include <lib/utils_def.h>
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/* DMC-620 memc register offsets */
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#define DMC620_MEMC_STATUS U(0x0000)
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#define DMC620_MEMC_CMD U(0x0008)
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/* Mask value to check the status of memc_cmd register */
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#define DMC620_MEMC_CMD_MASK U(0x00000007)
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/* memc_cmd register's action values */
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#define DMC620_MEMC_CMD_GO U(0x00000003)
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#define DMC620_MEMC_CMD_EXECUTE U(0x00000004)
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/* Address offsets of access address next region 0 registers */
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#define DMC620_ACC_ADDR_MIN_31_00_NEXT_BASE U(0x0080)
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#define DMC620_ACC_ADDR_MIN_47_32_NEXT_BASE U(0x0084)
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#define DMC620_ACC_ADDR_MAX_31_00_NEXT_BASE U(0x0088)
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#define DMC620_ACC_ADDR_MAX_47_32_NEXT_BASE U(0x008c)
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/* Length of one block of access address next register region */
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#define DMC620_ACC_ADDR_NEXT_SIZE U(0x0010)
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/* Address offsets of access address next registers */
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#define DMC620_ACC_ADDR_MIN_31_00_NEXT(region_no) \
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(DMC620_ACC_ADDR_MIN_31_00_NEXT_BASE + \
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((region_no) * DMC620_ACC_ADDR_NEXT_SIZE))
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#define DMC620_ACC_ADDR_MIN_47_32_NEXT(region_no) \
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(DMC620_ACC_ADDR_MIN_47_32_NEXT_BASE + \
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((region_no) * DMC620_ACC_ADDR_NEXT_SIZE))
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#define DMC620_ACC_ADDR_MAX_31_00_NEXT(region_no) \
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(DMC620_ACC_ADDR_MAX_31_00_NEXT_BASE + \
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((region_no) * DMC620_ACC_ADDR_NEXT_SIZE))
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#define DMC620_ACC_ADDR_MAX_47_32_NEXT(region_no) \
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(DMC620_ACC_ADDR_MAX_47_32_NEXT_BASE + \
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((region_no) * DMC620_ACC_ADDR_NEXT_SIZE))
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/* Number of TZC address regions in DMC-620 */
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#define DMC620_ACC_ADDR_COUNT U(8)
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/* Width of access address registers */
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#define DMC620_ACC_ADDR_WIDTH U(32)
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/* Peripheral ID registers offsets */
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#define DMC620_PERIPHERAL_ID_0 U(0x1fe0)
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/* Default values in id registers */
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#define DMC620_PERIPHERAL_ID_0_VALUE U(0x00000054)
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/* Secure access region attributes. */
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#define TZC_DMC620_REGION_NS_RD U(0x00000001)
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#define TZC_DMC620_REGION_NS_WR U(0x00000002)
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#define TZC_DMC620_REGION_NS_RDWR \
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(TZC_DMC620_REGION_NS_RD | TZC_DMC620_REGION_NS_WR)
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#define TZC_DMC620_REGION_S_RD U(0x00000004)
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#define TZC_DMC620_REGION_S_WR U(0x00000008)
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#define TZC_DMC620_REGION_S_RDWR \
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(TZC_DMC620_REGION_S_RD | TZC_DMC620_REGION_S_WR)
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#define TZC_DMC620_REGION_S_NS_RDWR \
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(TZC_DMC620_REGION_NS_RDWR | TZC_DMC620_REGION_S_RDWR)
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/*
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* Contains pointer to the base addresses of all the DMC-620 instances.
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* 'dmc_count' specifies the number of DMC base addresses contained in the
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* array pointed to by dmc_base.
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*/
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typedef struct tzc_dmc620_driver_data {
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const uintptr_t *dmc_base;
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const unsigned int dmc_count;
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} tzc_dmc620_driver_data_t;
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/*
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* Contains region base, region top addresses and corresponding attributes
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* for configuring TZC access region registers.
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*/
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typedef struct tzc_dmc620_acc_addr_data {
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const unsigned long long region_base;
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const unsigned long long region_top;
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const unsigned int sec_attr;
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} tzc_dmc620_acc_addr_data_t;
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/*
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* Contains platform specific data for configuring TZC region base and
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* region top address. 'acc_addr_count' specifies the number of
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* valid entries in 'plat_acc_addr_data' array.
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*/
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typedef struct tzc_dmc620_config_data {
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const tzc_dmc620_driver_data_t *plat_drv_data;
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const tzc_dmc620_acc_addr_data_t *plat_acc_addr_data;
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const uint8_t acc_addr_count;
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} tzc_dmc620_config_data_t;
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/* Function prototypes */
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void arm_tzc_dmc620_setup(const tzc_dmc620_config_data_t *plat_config_data);
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#endif /* TZC_DMC620_H */
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