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105 lines
2.9 KiB
105 lines
2.9 KiB
/*
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* Copyright (c) 2016 - 2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef EMMC_H
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#define EMMC_H
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#include <stdint.h>
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#include <common/debug.h>
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#include <platform_def.h>
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#include "emmc_chal_types.h"
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#include "emmc_chal_sd.h"
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#include "emmc_csl_sdprot.h"
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#include "emmc_csl_sdcmd.h"
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#include "emmc_pboot_hal_memory_drv.h"
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/* ------------------------------------------------------------------- */
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#define EXT_CSD_SIZE 512
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#ifdef PLAT_SD_MAX_READ_LENGTH
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#define SD_MAX_READ_LENGTH PLAT_SD_MAX_READ_LENGTH
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#ifdef USE_EMMC_LARGE_BLK_TRANSFER_LENGTH
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#define SD_MAX_BLK_TRANSFER_LENGTH 0x10000000
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#else
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#define SD_MAX_BLK_TRANSFER_LENGTH 0x1000
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#endif
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#else
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#define SD_MAX_READ_LENGTH EMMC_BLOCK_SIZE
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#define SD_MAX_BLK_TRANSFER_LENGTH EMMC_BLOCK_SIZE
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#endif
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struct emmc_global_buffer {
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union {
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uint8_t Ext_CSD_storage[EXT_CSD_SIZE];
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uint8_t tempbuf[SD_MAX_READ_LENGTH];
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} u;
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};
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struct emmc_global_vars {
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struct sd_card_data cardData;
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struct sd_handle sdHandle;
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struct sd_dev sdDevice;
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struct sd_card_info sdCard;
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unsigned int init_done;
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};
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#define ICFG_SDIO0_CAP0__SLOT_TYPE_R 27
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#define ICFG_SDIO0_CAP0__INT_MODE_R 26
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#define ICFG_SDIO0_CAP0__SYS_BUS_64BIT_R 25
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#define ICFG_SDIO0_CAP0__VOLTAGE_1P8V_R 24
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#define ICFG_SDIO0_CAP0__VOLTAGE_3P0V_R 23
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#define ICFG_SDIO0_CAP0__VOLTAGE_3P3V_R 22
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#define ICFG_SDIO0_CAP0__SUSPEND_RESUME_R 21
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#define ICFG_SDIO0_CAP0__SDMA_R 20
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#define ICFG_SDIO0_CAP0__HIGH_SPEED_R 19
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#define ICFG_SDIO0_CAP0__ADMA2_R 18
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#define ICFG_SDIO0_CAP0__EXTENDED_MEDIA_R 17
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#define ICFG_SDIO0_CAP0__MAX_BLOCK_LEN_R 15
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#define ICFG_SDIO0_CAP0__BASE_CLK_FREQ_R 7
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#define ICFG_SDIO0_CAP0__TIMEOUT_UNIT_R 6
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#define ICFG_SDIO0_CAP0__TIMEOUT_CLK_FREQ_R 0
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#define ICFG_SDIO0_CAP1__SPI_BLOCK_MODE_R 22
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#define ICFG_SDIO0_CAP1__SPI_MODE_R 21
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#define ICFG_SDIO0_CAP1__CLK_MULT_R 13
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#define ICFG_SDIO0_CAP1__RETUNING_MODE_R 11
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#define ICFG_SDIO0_CAP1__TUNE_SDR50_R 10
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#define ICFG_SDIO0_CAP1__TIME_RETUNE_R 6
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#define ICFG_SDIO0_CAP1__DRIVER_D_R 5
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#define ICFG_SDIO0_CAP1__DRIVER_C_R 4
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#define ICFG_SDIO0_CAP1__DRIVER_A_R 3
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#define ICFG_SDIO0_CAP1__DDR50_R 2
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#define ICFG_SDIO0_CAP1__SDR104_R 1
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#define ICFG_SDIO0_CAP1__SDR50_R 0
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#define SDIO0_CTRL_REGS_BASE_ADDR (SDIO0_EMMCSDXC_SYSADDR)
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#define SDIO0_IDM_RESET_CTRL_ADDR (SDIO_IDM0_IDM_RESET_CONTROL)
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#define EMMC_CTRL_REGS_BASE_ADDR SDIO0_CTRL_REGS_BASE_ADDR
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#define EMMC_IDM_RESET_CTRL_ADDR SDIO0_IDM_RESET_CTRL_ADDR
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#define EMMC_IDM_IO_CTRL_DIRECT_ADDR SDIO_IDM0_IO_CONTROL_DIRECT
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extern struct emmc_global_buffer *emmc_global_buf_ptr;
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extern struct emmc_global_vars *emmc_global_vars_ptr;
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#define EMMC_CARD_DETECT_TIMEOUT_MS 1200
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#define EMMC_CMD_TIMEOUT_MS 200
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#define EMMC_BUSY_CMD_TIMEOUT_MS 200
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#define EMMC_CLOCK_SETTING_TIMEOUT_MS 100
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#define EMMC_WFE_RETRY 40000
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#define EMMC_WFE_RETRY_DELAY_US 10
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#ifdef EMMC_DEBUG
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#define EMMC_TRACE INFO
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#else
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#define EMMC_TRACE(...)
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#endif
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#endif /* EMMC_H */
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