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692 lines
17 KiB
692 lines
17 KiB
/*
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* Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpuamu.h>
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#include <cpu_macros.S>
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#include <context.h>
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#include <neoverse_n1.h>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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.global neoverse_n1_errata_ic_trap_handler
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Erratum 1043202.
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* This applies to revision r0p0 and r1p0 of Neoverse N1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1043202_wa
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/* Compare x0 against revision r1p0 */
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mov x17, x30
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bl check_errata_1043202
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cbz x0, 1f
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/* Apply instruction patching sequence */
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ldr x0, =0x0
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msr CPUPSELR_EL3, x0
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ldr x0, =0xF3BF8F2F
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msr CPUPOR_EL3, x0
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ldr x0, =0xFFFFFFFF
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msr CPUPMR_EL3, x0
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ldr x0, =0x800200071
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msr CPUPCR_EL3, x0
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isb
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1:
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ret x17
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endfunc errata_n1_1043202_wa
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func check_errata_1043202
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1043202
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/* --------------------------------------------------
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* Disable speculative loads if Neoverse N1 supports
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* SSBS.
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*
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* Shall clobber: x0.
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* --------------------------------------------------
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*/
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func neoverse_n1_disable_speculative_loads
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/* Check if the PE implements SSBS */
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mrs x0, id_aa64pfr1_el1
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tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
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b.eq 1f
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/* Disable speculative loads */
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msr SSBS, xzr
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1:
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ret
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endfunc neoverse_n1_disable_speculative_loads
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Errata #1073348
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* This applies to revision r0p0 and r1p0 of Neoverse N1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1073348_wa
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/* Compare x0 against revision r1p0 */
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mov x17, x30
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bl check_errata_1073348
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cbz x0, 1f
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mrs x1, NEOVERSE_N1_CPUACTLR_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
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msr NEOVERSE_N1_CPUACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_n1_1073348_wa
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func check_errata_1073348
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1073348
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Errata #1130799
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* This applies to revision <=r2p0 of Neoverse N1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1130799_wa
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/* Compare x0 against revision r2p0 */
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mov x17, x30
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bl check_errata_1130799
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cbz x0, 1f
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mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
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msr NEOVERSE_N1_CPUACTLR2_EL1, x1
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1:
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ret x17
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endfunc errata_n1_1130799_wa
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func check_errata_1130799
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/* Applies to <=r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_1130799
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Errata #1165347
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* This applies to revision <=r2p0 of Neoverse N1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1165347_wa
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/* Compare x0 against revision r2p0 */
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mov x17, x30
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bl check_errata_1165347
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cbz x0, 1f
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mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
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orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
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msr NEOVERSE_N1_CPUACTLR2_EL1, x1
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1:
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ret x17
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endfunc errata_n1_1165347_wa
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func check_errata_1165347
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/* Applies to <=r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_1165347
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Errata #1207823
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* This applies to revision <=r2p0 of Neoverse N1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1207823_wa
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/* Compare x0 against revision r2p0 */
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mov x17, x30
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bl check_errata_1207823
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cbz x0, 1f
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mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
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msr NEOVERSE_N1_CPUACTLR2_EL1, x1
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1:
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ret x17
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endfunc errata_n1_1207823_wa
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func check_errata_1207823
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/* Applies to <=r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_1207823
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Errata #1220197
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* This applies to revision <=r2p0 of Neoverse N1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1220197_wa
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/* Compare x0 against revision r2p0 */
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mov x17, x30
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bl check_errata_1220197
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cbz x0, 1f
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mrs x1, NEOVERSE_N1_CPUECTLR_EL1
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orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK
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msr NEOVERSE_N1_CPUECTLR_EL1, x1
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1:
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ret x17
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endfunc errata_n1_1220197_wa
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func check_errata_1220197
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/* Applies to <=r2p0 */
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mov x1, #0x20
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b cpu_rev_var_ls
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endfunc check_errata_1220197
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Errata #1257314
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* This applies to revision <=r3p0 of Neoverse N1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1257314_wa
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/* Compare x0 against revision r3p0 */
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mov x17, x30
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bl check_errata_1257314
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cbz x0, 1f
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mrs x1, NEOVERSE_N1_CPUACTLR3_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
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msr NEOVERSE_N1_CPUACTLR3_EL1, x1
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1:
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ret x17
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endfunc errata_n1_1257314_wa
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func check_errata_1257314
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/* Applies to <=r3p0 */
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mov x1, #0x30
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b cpu_rev_var_ls
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endfunc check_errata_1257314
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Errata #1262606
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* This applies to revision <=r3p0 of Neoverse N1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1262606_wa
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/* Compare x0 against revision r3p0 */
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mov x17, x30
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bl check_errata_1262606
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cbz x0, 1f
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mrs x1, NEOVERSE_N1_CPUACTLR_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
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msr NEOVERSE_N1_CPUACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_n1_1262606_wa
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func check_errata_1262606
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/* Applies to <=r3p0 */
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mov x1, #0x30
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b cpu_rev_var_ls
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endfunc check_errata_1262606
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Errata #1262888
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* This applies to revision <=r3p0 of Neoverse N1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1262888_wa
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/* Compare x0 against revision r3p0 */
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mov x17, x30
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bl check_errata_1262888
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cbz x0, 1f
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mrs x1, NEOVERSE_N1_CPUECTLR_EL1
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orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
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msr NEOVERSE_N1_CPUECTLR_EL1, x1
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1:
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ret x17
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endfunc errata_n1_1262888_wa
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func check_errata_1262888
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/* Applies to <=r3p0 */
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mov x1, #0x30
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b cpu_rev_var_ls
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endfunc check_errata_1262888
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Errata #1275112
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* This applies to revision <=r3p0 of Neoverse N1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1275112_wa
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/* Compare x0 against revision r3p0 */
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mov x17, x30
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bl check_errata_1275112
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cbz x0, 1f
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mrs x1, NEOVERSE_N1_CPUACTLR_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
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msr NEOVERSE_N1_CPUACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_n1_1275112_wa
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func check_errata_1275112
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/* Applies to <=r3p0 */
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mov x1, #0x30
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b cpu_rev_var_ls
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endfunc check_errata_1275112
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Erratum 1315703.
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* This applies to revision <= r3p0 of Neoverse N1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1315703_wa
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/* Compare x0 against revision r3p1 */
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mov x17, x30
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bl check_errata_1315703
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cbz x0, 1f
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mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
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orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
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msr NEOVERSE_N1_CPUACTLR2_EL1, x0
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1:
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ret x17
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endfunc errata_n1_1315703_wa
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func check_errata_1315703
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/* Applies to everything <= r3p0. */
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mov x1, #0x30
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b cpu_rev_var_ls
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endfunc check_errata_1315703
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Erratum 1542419.
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* This applies to revisions r3p0 - r4p0 of Neoverse N1
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1542419_wa
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/* Compare x0 against revision r3p0 and r4p0 */
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mov x17, x30
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bl check_errata_1542419
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cbz x0, 1f
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/* Apply instruction patching sequence */
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ldr x0, =0x0
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msr CPUPSELR_EL3, x0
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ldr x0, =0xEE670D35
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msr CPUPOR_EL3, x0
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ldr x0, =0xFFFF0FFF
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msr CPUPMR_EL3, x0
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ldr x0, =0x08000020007D
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msr CPUPCR_EL3, x0
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isb
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1:
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ret x17
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endfunc errata_n1_1542419_wa
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func check_errata_1542419
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/* Applies to everything r3p0 - r4p0. */
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mov x1, #0x30
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mov x2, #0x40
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b cpu_rev_var_range
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endfunc check_errata_1542419
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Errata #1868343.
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* This applies to revision <= r4p0 of Neoverse N1.
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* This workaround is the same as the workaround for
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* errata 1262606 and 1275112 but applies to a wider
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* revision range.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1868343_wa
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/*
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* Compare x0 against revision r4p0
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*/
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mov x17, x30
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bl check_errata_1868343
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cbz x0, 1f
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mrs x1, NEOVERSE_N1_CPUACTLR_EL1
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orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
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msr NEOVERSE_N1_CPUACTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_n1_1868343_wa
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func check_errata_1868343
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/* Applies to everything <= r4p0 */
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mov x1, #0x40
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b cpu_rev_var_ls
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endfunc check_errata_1868343
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Errata #1946160.
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* This applies to revisions r3p0, r3p1, r4p0, and
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* r4p1 of Neoverse N1. It also exists in r0p0, r1p0,
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* and r2p0 but there is no fix in these revisions.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1946160_wa
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/*
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* Compare x0 against r3p0 - r4p1
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*/
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mov x17, x30
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bl check_errata_1946160
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cbz x0, 1f
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mov x0, #3
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msr S3_6_C15_C8_0, x0
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ldr x0, =0x10E3900002
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msr S3_6_C15_C8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_C15_C8_1, x0
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mov x0, #4
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msr S3_6_C15_C8_0, x0
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ldr x0, =0x10E3800082
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msr S3_6_C15_C8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_C15_C8_1, x0
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mov x0, #5
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msr S3_6_C15_C8_0, x0
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ldr x0, =0x10E3800200
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msr S3_6_C15_C8_2, x0
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ldr x0, =0x10FFF003E0
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_C15_C8_1, x0
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isb
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1:
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ret x17
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endfunc errata_n1_1946160_wa
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func check_errata_1946160
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/* Applies to r3p0 - r4p1. */
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mov x1, #0x30
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mov x2, #0x41
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b cpu_rev_var_range
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endfunc check_errata_1946160
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func neoverse_n1_reset_func
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mov x19, x30
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bl neoverse_n1_disable_speculative_loads
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/* Forces all cacheable atomic instructions to be near */
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mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
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orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
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msr NEOVERSE_N1_CPUACTLR2_EL1, x0
|
|
isb
|
|
|
|
bl cpu_get_rev_var
|
|
mov x18, x0
|
|
|
|
#if ERRATA_N1_1043202
|
|
mov x0, x18
|
|
bl errata_n1_1043202_wa
|
|
#endif
|
|
|
|
#if ERRATA_N1_1073348
|
|
mov x0, x18
|
|
bl errata_n1_1073348_wa
|
|
#endif
|
|
|
|
#if ERRATA_N1_1130799
|
|
mov x0, x18
|
|
bl errata_n1_1130799_wa
|
|
#endif
|
|
|
|
#if ERRATA_N1_1165347
|
|
mov x0, x18
|
|
bl errata_n1_1165347_wa
|
|
#endif
|
|
|
|
#if ERRATA_N1_1207823
|
|
mov x0, x18
|
|
bl errata_n1_1207823_wa
|
|
#endif
|
|
|
|
#if ERRATA_N1_1220197
|
|
mov x0, x18
|
|
bl errata_n1_1220197_wa
|
|
#endif
|
|
|
|
#if ERRATA_N1_1257314
|
|
mov x0, x18
|
|
bl errata_n1_1257314_wa
|
|
#endif
|
|
|
|
#if ERRATA_N1_1262606
|
|
mov x0, x18
|
|
bl errata_n1_1262606_wa
|
|
#endif
|
|
|
|
#if ERRATA_N1_1262888
|
|
mov x0, x18
|
|
bl errata_n1_1262888_wa
|
|
#endif
|
|
|
|
#if ERRATA_N1_1275112
|
|
mov x0, x18
|
|
bl errata_n1_1275112_wa
|
|
#endif
|
|
|
|
#if ERRATA_N1_1315703
|
|
mov x0, x18
|
|
bl errata_n1_1315703_wa
|
|
#endif
|
|
|
|
#if ERRATA_N1_1542419
|
|
mov x0, x18
|
|
bl errata_n1_1542419_wa
|
|
#endif
|
|
|
|
#if ERRATA_N1_1868343
|
|
mov x0, x18
|
|
bl errata_n1_1868343_wa
|
|
#endif
|
|
|
|
#if ERRATA_N1_1946160
|
|
mov x0, x18
|
|
bl errata_n1_1946160_wa
|
|
#endif
|
|
|
|
#if ENABLE_AMU
|
|
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
|
|
mrs x0, actlr_el3
|
|
orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
|
|
msr actlr_el3, x0
|
|
|
|
/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
|
|
mrs x0, actlr_el2
|
|
orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
|
|
msr actlr_el2, x0
|
|
|
|
/* Enable group0 counters */
|
|
mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK
|
|
msr CPUAMCNTENSET_EL0, x0
|
|
#endif
|
|
|
|
#if NEOVERSE_Nx_EXTERNAL_LLC
|
|
/* Some system may have External LLC, core needs to be made aware */
|
|
mrs x0, NEOVERSE_N1_CPUECTLR_EL1
|
|
orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
|
|
msr NEOVERSE_N1_CPUECTLR_EL1, x0
|
|
#endif
|
|
|
|
#if ERRATA_DSU_936184
|
|
bl errata_dsu_936184_wa
|
|
#endif
|
|
|
|
isb
|
|
ret x19
|
|
endfunc neoverse_n1_reset_func
|
|
|
|
/* ---------------------------------------------
|
|
* HW will do the cache maintenance while powering down
|
|
* ---------------------------------------------
|
|
*/
|
|
func neoverse_n1_core_pwr_dwn
|
|
/* ---------------------------------------------
|
|
* Enable CPU power down bit in power control register
|
|
* ---------------------------------------------
|
|
*/
|
|
mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
|
|
orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
|
|
msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
|
|
isb
|
|
ret
|
|
endfunc neoverse_n1_core_pwr_dwn
|
|
|
|
#if REPORT_ERRATA
|
|
/*
|
|
* Errata printing function for Neoverse N1. Must follow AAPCS.
|
|
*/
|
|
func neoverse_n1_errata_report
|
|
stp x8, x30, [sp, #-16]!
|
|
|
|
bl cpu_get_rev_var
|
|
mov x8, x0
|
|
|
|
/*
|
|
* Report all errata. The revision-variant information is passed to
|
|
* checking functions of each errata.
|
|
*/
|
|
report_errata ERRATA_N1_1043202, neoverse_n1, 1043202
|
|
report_errata ERRATA_N1_1073348, neoverse_n1, 1073348
|
|
report_errata ERRATA_N1_1130799, neoverse_n1, 1130799
|
|
report_errata ERRATA_N1_1165347, neoverse_n1, 1165347
|
|
report_errata ERRATA_N1_1207823, neoverse_n1, 1207823
|
|
report_errata ERRATA_N1_1220197, neoverse_n1, 1220197
|
|
report_errata ERRATA_N1_1257314, neoverse_n1, 1257314
|
|
report_errata ERRATA_N1_1262606, neoverse_n1, 1262606
|
|
report_errata ERRATA_N1_1262888, neoverse_n1, 1262888
|
|
report_errata ERRATA_N1_1275112, neoverse_n1, 1275112
|
|
report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
|
|
report_errata ERRATA_N1_1542419, neoverse_n1, 1542419
|
|
report_errata ERRATA_N1_1868343, neoverse_n1, 1868343
|
|
report_errata ERRATA_N1_1946160, neoverse_n1, 1946160
|
|
report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
|
|
|
|
ldp x8, x30, [sp], #16
|
|
ret
|
|
endfunc neoverse_n1_errata_report
|
|
#endif
|
|
|
|
/*
|
|
* Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB
|
|
* inner-shareable invalidation to an arbitrary address followed by a DSB.
|
|
*
|
|
* x1: Exception Syndrome
|
|
*/
|
|
func neoverse_n1_errata_ic_trap_handler
|
|
cmp x1, #NEOVERSE_N1_EC_IC_TRAP
|
|
b.ne 1f
|
|
tlbi vae3is, xzr
|
|
dsb sy
|
|
|
|
# Skip the IC instruction itself
|
|
mrs x3, elr_el3
|
|
add x3, x3, #4
|
|
msr elr_el3, x3
|
|
|
|
ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
|
|
ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
|
|
ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
|
|
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
|
|
|
#if IMAGE_BL31 && RAS_EXTENSION
|
|
/*
|
|
* Issue Error Synchronization Barrier to synchronize SErrors before
|
|
* exiting EL3. We're running with EAs unmasked, so any synchronized
|
|
* errors would be taken immediately; therefore no need to inspect
|
|
* DISR_EL1 register.
|
|
*/
|
|
esb
|
|
#endif
|
|
exception_return
|
|
1:
|
|
ret
|
|
endfunc neoverse_n1_errata_ic_trap_handler
|
|
|
|
/* ---------------------------------------------
|
|
* This function provides neoverse_n1 specific
|
|
* register information for crash reporting.
|
|
* It needs to return with x6 pointing to
|
|
* a list of register names in ascii and
|
|
* x8 - x15 having values of registers to be
|
|
* reported.
|
|
* ---------------------------------------------
|
|
*/
|
|
.section .rodata.neoverse_n1_regs, "aS"
|
|
neoverse_n1_regs: /* The ascii list of register names to be reported */
|
|
.asciz "cpuectlr_el1", ""
|
|
|
|
func neoverse_n1_cpu_reg_dump
|
|
adr x6, neoverse_n1_regs
|
|
mrs x8, NEOVERSE_N1_CPUECTLR_EL1
|
|
ret
|
|
endfunc neoverse_n1_cpu_reg_dump
|
|
|
|
declare_cpu_ops_eh neoverse_n1, NEOVERSE_N1_MIDR, \
|
|
neoverse_n1_reset_func, \
|
|
neoverse_n1_errata_ic_trap_handler, \
|
|
neoverse_n1_core_pwr_dwn
|