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171 lines
5.4 KiB
171 lines
5.4 KiB
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/bl_common.h>
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#include <common/interrupt_props.h>
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#include <drivers/arm/gicv2.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include "aml_private.h"
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/*
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* Placeholder variables for copying the arguments that have been passed to
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* BL31 from BL2.
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*/
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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static image_info_t bl30_image_info;
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static image_info_t bl301_image_info;
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* the security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type. A NULL pointer is returned
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* if the image does not exist.
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******************************************************************************/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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next_image_info = (type == NON_SECURE) ?
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&bl33_image_ep_info : &bl32_image_ep_info;
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/* None of the images can have 0x0 as the entrypoint. */
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if (next_image_info->pc != 0U)
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return next_image_info;
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return NULL;
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}
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/*******************************************************************************
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* Perform any BL31 early platform setup. Here is an opportunity to copy
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* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before
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* they are lost (potentially). This needs to be done before the MMU is
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* initialized so that the memory layout can be used while creating page
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* tables. BL2 has flushed this information to memory, so we are guaranteed
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* to pick up good data.
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******************************************************************************/
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struct axg_bl31_param {
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param_header_t h;
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image_info_t *bl31_image_info;
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entry_point_info_t *bl32_ep_info;
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image_info_t *bl32_image_info;
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entry_point_info_t *bl33_ep_info;
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image_info_t *bl33_image_info;
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image_info_t *scp_image_info[];
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};
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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struct axg_bl31_param *from_bl2;
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/* Initialize the console to provide early debug support */
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aml_console_init();
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from_bl2 = (struct axg_bl31_param *)arg0;
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/* Check params passed from BL2 are not NULL. */
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assert(from_bl2 != NULL);
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assert(from_bl2->h.type == PARAM_BL31);
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assert(from_bl2->h.version >= VERSION_1);
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/*
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* Copy BL32 and BL33 entry point information. It is stored in Secure
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* RAM, in BL2's address space.
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*/
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bl32_image_ep_info = *from_bl2->bl32_ep_info;
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bl33_image_ep_info = *from_bl2->bl33_ep_info;
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#if AML_USE_ATOS
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/*
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* BL2 is unconditionally setting 0 (OPTEE_AARCH64) in arg0 even when
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* the BL32 image is 32bit (OPTEE_AARCH32). This is causing the boot to
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* hang when ATOS (32bit Amlogic BL32 binary-only TEE OS) is used.
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*
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* Hardcode to OPTEE_AARCH32 / MODE_RW_32.
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*/
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bl32_image_ep_info.args.arg0 = MODE_RW_32;
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#endif
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if (bl33_image_ep_info.pc == 0U) {
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ERROR("BL31: BL33 entrypoint not obtained from BL2\n");
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panic();
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}
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bl30_image_info = *from_bl2->scp_image_info[0];
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bl301_image_info = *from_bl2->scp_image_info[1];
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}
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void bl31_plat_arch_setup(void)
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{
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aml_setup_page_tables();
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enable_mmu_el3(0);
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}
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static inline bool axg_scp_ready(void)
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{
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return AML_AO_RTI_SCP_IS_READY(mmio_read_32(AML_AO_RTI_SCP_STAT));
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}
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static inline void axg_scp_boot(void)
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{
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aml_scpi_upload_scp_fw(bl30_image_info.image_base,
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bl30_image_info.image_size, 0);
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aml_scpi_upload_scp_fw(bl301_image_info.image_base,
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bl301_image_info.image_size, 1);
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while (!axg_scp_ready())
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;
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}
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/*******************************************************************************
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* GICv2 driver setup information
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******************************************************************************/
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static const interrupt_prop_t axg_interrupt_props[] = {
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INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
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};
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static const gicv2_driver_data_t axg_gic_data = {
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.gicd_base = AML_GICD_BASE,
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.gicc_base = AML_GICC_BASE,
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.interrupt_props = axg_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(axg_interrupt_props)
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};
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void bl31_platform_setup(void)
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{
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aml_mhu_secure_init();
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gicv2_driver_init(&axg_gic_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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axg_scp_boot();
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}
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