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136 lines
4.5 KiB
136 lines
4.5 KiB
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef G12A_DEF_H
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#define G12A_DEF_H
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#include <lib/utils_def.h>
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/*******************************************************************************
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* System oscillator
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******************************************************************************/
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#define AML_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */
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/*******************************************************************************
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* Memory regions
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******************************************************************************/
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#define AML_HDCP_RX_BASE UL(0xFFE0D000)
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#define AML_HDCP_RX_SIZE UL(0x00002000)
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#define AML_HDCP_TX_BASE UL(0xFFE01000)
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#define AML_HDCP_TX_SIZE UL(0x00001000)
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#define AML_NS_SHARE_MEM_BASE UL(0x05000000)
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#define AML_NS_SHARE_MEM_SIZE UL(0x00100000)
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#define AML_SEC_SHARE_MEM_BASE UL(0x05200000)
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#define AML_SEC_SHARE_MEM_SIZE UL(0x00100000)
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#define AML_GIC_DEVICE_BASE UL(0xFFC00000)
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#define AML_GIC_DEVICE_SIZE UL(0x00008000)
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#define AML_NSDRAM0_BASE UL(0x01000000)
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#define AML_NSDRAM0_SIZE UL(0x0F000000)
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#define BL31_BASE UL(0x05100000)
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#define BL31_SIZE UL(0x00100000)
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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/* Shared memory used for SMC services */
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#define AML_SHARE_MEM_INPUT_BASE UL(0x050FE000)
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#define AML_SHARE_MEM_OUTPUT_BASE UL(0x050FF000)
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#define AML_SEC_DEVICE0_BASE UL(0xFFD00000)
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#define AML_SEC_DEVICE0_SIZE UL(0x00026000)
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#define AML_SEC_DEVICE1_BASE UL(0xFF800000)
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#define AML_SEC_DEVICE1_SIZE UL(0x0000A000)
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#define AML_TZRAM_BASE UL(0xFFFA0000)
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#define AML_TZRAM_SIZE UL(0x00048000)
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/* Mailboxes */
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#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xFFFE7800)
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#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xFFFE7A00)
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#define AML_PSCI_MAILBOX_BASE UL(0xFFFE7F00)
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#define AML_SEC_DEVICE2_BASE UL(0xFF620000)
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#define AML_SEC_DEVICE2_SIZE UL(0x00028000)
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/*******************************************************************************
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* GIC-400 and interrupt handling related constants
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******************************************************************************/
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#define AML_GICD_BASE UL(0xFFC01000)
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#define AML_GICC_BASE UL(0xFFC02000)
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#define IRQ_SEC_PHY_TIMER 29
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#define IRQ_SEC_SGI_0 8
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#define IRQ_SEC_SGI_1 9
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#define IRQ_SEC_SGI_2 10
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#define IRQ_SEC_SGI_3 11
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#define IRQ_SEC_SGI_4 12
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#define IRQ_SEC_SGI_5 13
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#define IRQ_SEC_SGI_6 14
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#define IRQ_SEC_SGI_7 15
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#define IRQ_SEC_SGI_8 16
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/*******************************************************************************
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* UART definitions
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******************************************************************************/
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#define AML_UART0_AO_BASE UL(0xFF803000)
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#define AML_UART0_AO_CLK_IN_HZ AML_OSC24M_CLK_IN_HZ
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#define AML_UART_BAUDRATE U(115200)
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/*******************************************************************************
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* Memory-mapped I/O Registers
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******************************************************************************/
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#define AML_AO_TIMESTAMP_CNTL UL(0xFF8000B4)
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#define AML_SYS_CPU_CFG7 UL(0xFF634664)
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#define AML_AO_RTI_STATUS_REG3 UL(0xFF80001C)
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#define AML_AO_RTI_SCP_STAT UL(0xFF80023C)
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#define AML_AO_RTI_SCP_READY_OFF U(0x14)
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#define AML_A0_RTI_SCP_READY_MASK U(3)
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#define AML_AO_RTI_SCP_IS_READY(v) \
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((((v) >> AML_AO_RTI_SCP_READY_OFF) & \
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AML_A0_RTI_SCP_READY_MASK) == AML_A0_RTI_SCP_READY_MASK)
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#define AML_HIU_MAILBOX_SET_0 UL(0xFF63C404)
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#define AML_HIU_MAILBOX_STAT_0 UL(0xFF63C408)
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#define AML_HIU_MAILBOX_CLR_0 UL(0xFF63C40C)
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#define AML_HIU_MAILBOX_SET_3 UL(0xFF63C428)
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#define AML_HIU_MAILBOX_STAT_3 UL(0xFF63C42C)
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#define AML_HIU_MAILBOX_CLR_3 UL(0xFF63C430)
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#define AML_SHA_DMA_BASE UL(0xFF63E000)
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#define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08)
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#define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x28)
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/*******************************************************************************
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* System Monitor Call IDs and arguments
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******************************************************************************/
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#define AML_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020)
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#define AML_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021)
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#define AML_SM_EFUSE_READ U(0x82000030)
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#define AML_SM_EFUSE_USER_MAX U(0x82000033)
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#define AML_SM_JTAG_ON U(0x82000040)
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#define AML_SM_JTAG_OFF U(0x82000041)
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#define AML_SM_GET_CHIP_ID U(0x82000044)
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#define AML_JTAG_STATE_ON U(0)
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#define AML_JTAG_STATE_OFF U(1)
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#define AML_JTAG_M3_AO U(0)
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#define AML_JTAG_M3_EE U(1)
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#define AML_JTAG_A53_AO U(2)
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#define AML_JTAG_A53_EE U(3)
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#endif /* G12A_DEF_H */
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