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159 lines
5.6 KiB
159 lines
5.6 KiB
/*
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* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <drivers/arm/nic_400.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/arm/soc/common/soc_css.h>
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#include <plat/common/platform.h>
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#include "juno_tzmp1_def.h"
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#ifdef JUNO_TZMP1
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/*
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* Protect buffer for VPU/GPU/DPU memory usage with hardware protection
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* enabled. Propose 224MB video output, 96 MB video input and 32MB video
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* private.
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*
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* Ind Memory Range Caption S_ATTR NS_ATTR
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* 1 0x080000000 - 0x0E7FFFFFF ARM_NS_DRAM1 NONE RDWR | MEDIA_RW
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* 2 0x0E8000000 - 0x0F5FFFFFF JUNO_MEDIA_TZC_PROT_DRAM1 NONE MEDIA_RW | AP_WR
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* 3 0x0F6000000 - 0x0FBFFFFFF JUNO_VPU_TZC_PROT_DRAM1 RDWR VPU_PROT_RW
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* 4 0x0FC000000 - 0x0FDFFFFFF JUNO_VPU_TZC_PRIV_DRAM1 RDWR VPU_PRIV_RW
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* 5 0x0FE000000 - 0x0FEFFFFFF JUNO_AP_TZC_SHARE_DRAM1 NONE RDWR | MEDIA_RW
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* 6 0x0FF000000 - 0x0FFFFFFFF ARM_AP_TZC_DRAM1 RDWR NONE
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* 7 0x880000000 - 0x9FFFFFFFF ARM_DRAM2 NONE RDWR | MEDIA_RW
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*
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* Memory regions are neighbored to save limited TZC regions. Calculation
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* started from ARM_TZC_SHARE_DRAM1 since it is known and fixed for both
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* protected-enabled and protected-disabled settings.
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*
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* Video private buffer aheads of ARM_TZC_SHARE_DRAM1
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*/
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static const arm_tzc_regions_info_t juno_tzmp1_tzc_regions[] = {
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{ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},
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{JUNO_NS_DRAM1_PT1_BASE, JUNO_NS_DRAM1_PT1_END,
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TZC_REGION_S_NONE, JUNO_MEDIA_TZC_NS_DEV_ACCESS},
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{JUNO_MEDIA_TZC_PROT_DRAM1_BASE, JUNO_MEDIA_TZC_PROT_DRAM1_END,
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TZC_REGION_S_NONE, JUNO_MEDIA_TZC_PROT_ACCESS},
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{JUNO_VPU_TZC_PROT_DRAM1_BASE, JUNO_VPU_TZC_PROT_DRAM1_END,
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TZC_REGION_S_RDWR, JUNO_VPU_TZC_PROT_ACCESS},
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{JUNO_VPU_TZC_PRIV_DRAM1_BASE, JUNO_VPU_TZC_PRIV_DRAM1_END,
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TZC_REGION_S_RDWR, JUNO_VPU_TZC_PRIV_ACCESS},
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{JUNO_AP_TZC_SHARE_DRAM1_BASE, JUNO_AP_TZC_SHARE_DRAM1_END,
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TZC_REGION_S_NONE, JUNO_MEDIA_TZC_NS_DEV_ACCESS},
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{ARM_DRAM2_BASE, ARM_DRAM2_END,
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TZC_REGION_S_NONE, JUNO_MEDIA_TZC_NS_DEV_ACCESS},
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{},
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};
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/*******************************************************************************
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* Program dp650 to configure NSAID value for protected mode.
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******************************************************************************/
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static void init_dp650(void)
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{
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mmio_write_32(DP650_BASE + DP650_PROT_NSAID_OFFSET,
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DP650_PROT_NSAID_CONFIG);
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}
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/*******************************************************************************
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* Program v550 to configure NSAID value for protected mode.
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******************************************************************************/
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static void init_v550(void)
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{
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/*
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* bits[31:28] is for PRIVATE,
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* bits[27:24] is for OUTBUF,
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* bits[23:20] is for PROTECTED.
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*/
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mmio_write_32(V550_BASE + V550_PROTCTRL_OFFSET, V550_PROTCTRL_CONFIG);
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}
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#endif /* JUNO_TZMP1 */
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/*******************************************************************************
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* Set up the MMU-401 SSD tables. The power-on configuration has all stream IDs
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* assigned to Non-Secure except some for the DMA-330. Assign those back to the
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* Non-Secure world as well, otherwise EL1 may end up erroneously generating
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* (untranslated) Secure transactions if it turns the SMMU on.
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******************************************************************************/
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static void init_mmu401(void)
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{
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uint32_t reg = mmio_read_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET);
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reg |= 0x1FF;
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mmio_write_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET, reg);
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}
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/*******************************************************************************
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* Program CSS-NIC400 to allow non-secure access to some CSS regions.
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******************************************************************************/
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static void css_init_nic400(void)
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{
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/* Note: This is the NIC-400 device on the CSS */
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mmio_write_32(PLAT_SOC_CSS_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE),
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~0);
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}
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/*******************************************************************************
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* Initialize debug configuration.
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******************************************************************************/
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static void init_debug_cfg(void)
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{
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#if !DEBUG
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/* Set internal drive selection for SPIDEN. */
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mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_SET,
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1U << SPIDEN_SEL_SET_SHIFT);
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/* Drive SPIDEN LOW to disable invasive debug of secure state. */
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mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR,
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1U << SPIDEN_INT_CLR_SHIFT);
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#endif
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}
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/*******************************************************************************
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* Initialize the secure environment.
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******************************************************************************/
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void plat_arm_security_setup(void)
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{
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/* Initialize debug configuration */
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init_debug_cfg();
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/* Initialize the TrustZone Controller */
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#ifdef JUNO_TZMP1
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arm_tzc400_setup(PLAT_ARM_TZC_BASE, juno_tzmp1_tzc_regions);
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INFO("TZC protected shared memory base address for TZMP usecase: %p\n",
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(void *)JUNO_AP_TZC_SHARE_DRAM1_BASE);
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INFO("TZC protected shared memory end address for TZMP usecase: %p\n",
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(void *)JUNO_AP_TZC_SHARE_DRAM1_END);
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#else
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arm_tzc400_setup(PLAT_ARM_TZC_BASE, NULL);
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#endif
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/* Do ARM CSS internal NIC setup */
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css_init_nic400();
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/* Do ARM CSS SoC security setup */
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soc_css_security_setup();
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/* Initialize the SMMU SSD tables */
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init_mmu401();
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#ifdef JUNO_TZMP1
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init_dp650();
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init_v550();
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#endif
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}
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#if TRUSTED_BOARD_BOOT
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int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
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{
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assert(heap_addr != NULL);
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assert(heap_size != NULL);
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return arm_get_mbedtls_heap(heap_addr, heap_size);
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}
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#endif
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