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363 lines
13 KiB
363 lines
13 KiB
/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/css/css_scp.h>
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#include <lib/cassert.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/arm/css/common/css_pm.h>
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/* Allow CSS platforms to override `plat_arm_psci_pm_ops` */
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#pragma weak plat_arm_psci_pm_ops
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#if ARM_RECOM_STATE_ID_ENC
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/*
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* The table storing the valid idle power states. Ensure that the
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* array entries are populated in ascending order of state-id to
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* enable us to use binary search during power state validation.
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* The table must be terminated by a NULL entry.
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*/
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const unsigned int arm_pm_idle_states[] = {
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/* State-id - 0x001 */
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arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
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ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY),
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/* State-id - 0x002 */
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arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN,
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ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN),
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/* State-id - 0x022 */
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arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF,
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ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN),
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#if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1
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/* State-id - 0x222 */
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arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF,
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ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN),
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#endif
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0,
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};
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#endif /* __ARM_RECOM_STATE_ID_ENC__ */
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/*
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* All the power management helpers in this file assume at least cluster power
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* level is supported.
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*/
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CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1,
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assert_max_pwr_lvl_supported_mismatch);
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/*
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* Ensure that the PLAT_MAX_PWR_LVL is not greater than CSS_SYSTEM_PWR_DMN_LVL
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* assumed by the CSS layer.
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*/
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CASSERT(PLAT_MAX_PWR_LVL <= CSS_SYSTEM_PWR_DMN_LVL,
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assert_max_pwr_lvl_higher_than_css_sys_lvl);
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/*******************************************************************************
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* Handler called when a power domain is about to be turned on. The
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* level and mpidr determine the affinity instance.
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******************************************************************************/
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int css_pwr_domain_on(u_register_t mpidr)
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{
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css_scp_on(mpidr);
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return PSCI_E_SUCCESS;
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}
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static void css_pwr_domain_on_finisher_common(
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const psci_power_state_t *target_state)
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{
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assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
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/*
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* Perform the common cluster specific operations i.e enable coherency
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* if this cluster was off.
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*/
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if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
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plat_arm_interconnect_enter_coherency();
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}
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/*******************************************************************************
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* Handler called when a power level has just been powered on after
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* being turned off earlier. The target_state encodes the low power state that
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* each level has woken up from. This handler would never be invoked with
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* the system power domain uninitialized as either the primary would have taken
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* care of it as part of cold boot or the first core awakened from system
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* suspend would have already initialized it.
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******************************************************************************/
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void css_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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/* Assert that the system power domain need not be initialized */
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assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN);
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css_pwr_domain_on_finisher_common(target_state);
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}
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/*******************************************************************************
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* Handler called when a power domain has just been powered on and the cpu
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* and its cluster are fully participating in coherent transaction on the
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* interconnect. Data cache must be enabled for CPU at this point.
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******************************************************************************/
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void css_pwr_domain_on_finish_late(const psci_power_state_t *target_state)
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{
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/* Program the gic per-cpu distributor or re-distributor interface */
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plat_arm_gic_pcpu_init();
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/* Enable the gic cpu interface */
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plat_arm_gic_cpuif_enable();
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}
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/*******************************************************************************
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* Common function called while turning a cpu off or suspending it. It is called
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* from css_off() or css_suspend() when these functions in turn are called for
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* power domain at the highest power level which will be powered down. It
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* performs the actions common to the OFF and SUSPEND calls.
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******************************************************************************/
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static void css_power_down_common(const psci_power_state_t *target_state)
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{
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/* Prevent interrupts from spuriously waking up this cpu */
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plat_arm_gic_cpuif_disable();
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/* Turn redistributor off */
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plat_arm_gic_redistif_off();
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/* Cluster is to be turned off, so disable coherency */
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if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
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plat_arm_interconnect_exit_coherency();
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#if HW_ASSISTED_COHERENCY
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uint32_t reg;
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/*
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* If we have determined this core to be the last man standing and we
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* intend to power down the cluster proactively, we provide a hint to
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* the power controller that cluster power is not required when all
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* cores are powered down.
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* Note that this is only an advisory to power controller and is supported
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* by SoCs with DynamIQ Shared Units only.
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*/
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reg = read_clusterpwrdn();
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/* Clear and set bit 0 : Cluster power not required */
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reg &= ~DSU_CLUSTER_PWR_MASK;
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reg |= DSU_CLUSTER_PWR_OFF;
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write_clusterpwrdn(reg);
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#endif
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}
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}
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/*******************************************************************************
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* Handler called when a power domain is about to be turned off. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void css_pwr_domain_off(const psci_power_state_t *target_state)
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{
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assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
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css_power_down_common(target_state);
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css_scp_off(target_state);
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}
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/*******************************************************************************
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* Handler called when a power domain is about to be suspended. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void css_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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/*
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* CSS currently supports retention only at cpu level. Just return
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* as nothing is to be done for retention.
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*/
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if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
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return;
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assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
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css_power_down_common(target_state);
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/* Perform system domain state saving if issuing system suspend */
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if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) {
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arm_system_pwr_domain_save();
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/* Power off the Redistributor after having saved its context */
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plat_arm_gic_redistif_off();
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}
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css_scp_suspend(target_state);
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}
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/*******************************************************************************
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* Handler called when a power domain has just been powered on after
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* having been suspended earlier. The target_state encodes the low power state
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* that each level has woken up from.
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* TODO: At the moment we reuse the on finisher and reinitialize the secure
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* context. Need to implement a separate suspend finisher.
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******************************************************************************/
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void css_pwr_domain_suspend_finish(
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const psci_power_state_t *target_state)
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{
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/* Return as nothing is to be done on waking up from retention. */
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if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
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return;
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/* Perform system domain restore if woken up from system suspend */
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if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF)
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/*
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* At this point, the Distributor must be powered on to be ready
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* to have its state restored. The Redistributor will be powered
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* on as part of gicv3_rdistif_init_restore.
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*/
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arm_system_pwr_domain_resume();
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css_pwr_domain_on_finisher_common(target_state);
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/* Enable the gic cpu interface */
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plat_arm_gic_cpuif_enable();
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}
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/*******************************************************************************
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* Handlers to shutdown/reboot the system
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******************************************************************************/
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void __dead2 css_system_off(void)
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{
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css_scp_sys_shutdown();
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}
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void __dead2 css_system_reset(void)
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{
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css_scp_sys_reboot();
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}
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/*******************************************************************************
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* Handler called when the CPU power domain is about to enter standby.
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******************************************************************************/
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void css_cpu_standby(plat_local_state_t cpu_state)
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{
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unsigned int scr;
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assert(cpu_state == ARM_LOCAL_STATE_RET);
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scr = read_scr_el3();
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/*
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* Enable the Non secure interrupt to wake the CPU.
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* In GICv3 affinity routing mode, the non secure group1 interrupts use
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* the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ.
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* Enabling both the bits works for both GICv2 mode and GICv3 affinity
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* routing mode.
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*/
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write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
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isb();
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dsb();
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wfi();
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/*
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* Restore SCR to the original value, synchronisation of scr_el3 is
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* done by eret while el3_exit to save some execution cycles.
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*/
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write_scr_el3(scr);
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}
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/*******************************************************************************
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* Handler called to return the 'req_state' for system suspend.
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******************************************************************************/
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void css_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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unsigned int i;
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/*
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* System Suspend is supported only if the system power domain node
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* is implemented.
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*/
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assert(PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL);
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for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF;
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}
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/*******************************************************************************
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* Handler to query CPU/cluster power states from SCP
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******************************************************************************/
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int css_node_hw_state(u_register_t mpidr, unsigned int power_level)
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{
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return css_scp_get_power_state(mpidr, power_level);
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}
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/*
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* The system power domain suspend is only supported only via
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* PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain
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* will be downgraded to the lower level.
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*/
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static int css_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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int rc;
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rc = arm_validate_power_state(power_state, req_state);
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/*
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* Ensure that we don't overrun the pwr_domain_state array in the case
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* where the platform supported max power level is less than the system
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* power level
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*/
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#if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL)
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/*
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* Ensure that the system power domain level is never suspended
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* via PSCI CPU SUSPEND API. Currently system suspend is only
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* supported via PSCI SYSTEM SUSPEND API.
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*/
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req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] =
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ARM_LOCAL_STATE_RUN;
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#endif
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return rc;
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}
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/*
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* Custom `translate_power_state_by_mpidr` handler for CSS. Unlike in the
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* `css_validate_power_state`, we do not downgrade the system power
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* domain level request in `power_state` as it will be used to query the
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* PSCI_STAT_COUNT/RESIDENCY at the system power domain level.
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*/
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static int css_translate_power_state_by_mpidr(u_register_t mpidr,
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unsigned int power_state,
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psci_power_state_t *output_state)
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{
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return arm_validate_power_state(power_state, output_state);
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}
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/*******************************************************************************
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* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
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* platform will take care of registering the handlers with PSCI.
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******************************************************************************/
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plat_psci_ops_t plat_arm_psci_pm_ops = {
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.pwr_domain_on = css_pwr_domain_on,
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.pwr_domain_on_finish = css_pwr_domain_on_finish,
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.pwr_domain_on_finish_late = css_pwr_domain_on_finish_late,
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.pwr_domain_off = css_pwr_domain_off,
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.cpu_standby = css_cpu_standby,
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.pwr_domain_suspend = css_pwr_domain_suspend,
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.pwr_domain_suspend_finish = css_pwr_domain_suspend_finish,
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.system_off = css_system_off,
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.system_reset = css_system_reset,
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.validate_power_state = css_validate_power_state,
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.validate_ns_entrypoint = arm_validate_psci_entrypoint,
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.translate_power_state_by_mpidr = css_translate_power_state_by_mpidr,
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.get_node_hw_state = css_node_hw_state,
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.get_sys_suspend_power_state = css_get_sys_suspend_power_state,
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#if defined(PLAT_ARM_MEM_PROT_ADDR)
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.mem_protect_chk = arm_psci_mem_protect_chk,
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.read_mem_protect = arm_psci_read_mem_protect,
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.write_mem_protect = arm_nor_psci_write_mem_protect,
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#endif
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#if CSS_USE_SCMI_SDS_DRIVER
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.system_reset2 = css_system_reset2,
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#endif
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};
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