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248 lines
8.1 KiB
248 lines
8.1 KiB
/*
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* Copyright (c) 2019-2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SDIO_H
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#define SDIO_H
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#include <stdbool.h>
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#define SR_IPROC_SDIO0_CFG_BASE 0x689006e4
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#define SR_IPROC_SDIO0_SID_BASE 0x68900b00
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#define SR_IPROC_SDIO0_PAD_BASE 0x68a4017c
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#define SR_IPROC_SDIO0_IOCTRL_BASE 0x68e02408
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#define SR_IPROC_SDIO1_CFG_BASE 0x68900734
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#define SR_IPROC_SDIO1_SID_BASE 0x68900b08
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#define SR_IPROC_SDIO1_PAD_BASE 0x68a401b4
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#define SR_IPROC_SDIO1_IOCTRL_BASE 0x68e03408
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#define NS3Z_IPROC_SDIO0_CFG_BASE 0x68a20540
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#define NS3Z_IPROC_SDIO0_SID_BASE 0x68900b00
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#define NS3Z_IPROC_SDIO0_TP_OUT_SEL 0x68a20308
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#define NS3Z_IPROC_SDIO0_PAD_BASE 0x68a20500
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#define NS3Z_IPROC_SDIO0_IOCTRL_BASE 0x68e02408
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#define PHY_BYPASS BIT(14)
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#define LEGACY_EN BIT(31)
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#define PHY_DISABLE (LEGACY_EN | PHY_BYPASS)
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#define NS3Z_IPROC_SDIO1_CFG_BASE 0x68a30540
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#define NS3Z_IPROC_SDIO1_SID_BASE 0x68900b08
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#define NS3Z_IPROC_SDIO1_PAD_BASE 0x68a30500
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#define NS3Z_IPROC_SDIO1_IOCTRL_BASE 0x68e03408
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#define ICFG_SDIO_CAP0 0x10
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#define ICFG_SDIO_CAP1 0x14
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#define ICFG_SDIO_STRAPSTATUS_0 0x0
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#define ICFG_SDIO_STRAPSTATUS_1 0x4
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#define ICFG_SDIO_STRAPSTATUS_2 0x8
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#define ICFG_SDIO_STRAPSTATUS_3 0xc
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#define ICFG_SDIO_STRAPSTATUS_4 0x18
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#define ICFG_SDIO_SID_ARADDR 0x0
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#define ICFG_SDIO_SID_AWADDR 0x4
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#define ICFG_SDIOx_CAP0__SLOT_TYPE_MASK 0x3
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#define ICFG_SDIOx_CAP0__SLOT_TYPE_SHIFT 27
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#define ICFG_SDIOx_CAP0__INT_MODE_SHIFT 26
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#define ICFG_SDIOx_CAP0__SYS_BUS_64BIT_SHIFT 25
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#define ICFG_SDIOx_CAP0__VOLTAGE_1P8V_SHIFT 24
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#define ICFG_SDIOx_CAP0__VOLTAGE_3P0V_SHIFT 23
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#define ICFG_SDIOx_CAP0__VOLTAGE_3P3V_SHIFT 22
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#define ICFG_SDIOx_CAP0__SUSPEND_RESUME_SHIFT 21
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#define ICFG_SDIOx_CAP0__SDMA_SHIFT 20
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#define ICFG_SDIOx_CAP0__HIGH_SPEED_SHIFT 19
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#define ICFG_SDIOx_CAP0__ADMA2_SHIFT 18
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#define ICFG_SDIOx_CAP0__EXTENDED_MEDIA_SHIFT 17
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#define ICFG_SDIOx_CAP0__MAX_BLOCK_LEN_MASK 0x3
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#define ICFG_SDIOx_CAP0__MAX_BLOCK_LEN_SHIFT 15
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#define ICFG_SDIOx_CAP0__BASE_CLK_FREQ_MASK 0xff
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#define ICFG_SDIOx_CAP0__BASE_CLK_FREQ_SHIFT 7
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#define ICFG_SDIOx_CAP0__TIMEOUT_UNIT_SHIFT 6
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#define ICFG_SDIOx_CAP0__TIMEOUT_CLK_FREQ_MASK 0x3f
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#define ICFG_SDIOx_CAP0__TIMEOUT_CLK_FREQ_SHIFT 0
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#define ICFG_SDIOx_CAP1__SPI_BLOCK_MODE_SHIFT 22
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#define ICFG_SDIOx_CAP1__SPI_MODE_SHIFT 21
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#define ICFG_SDIOx_CAP1__CLK_MULT_MASK 0xff
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#define ICFG_SDIOx_CAP1__CLK_MULT_SHIFT 13
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#define ICFG_SDIOx_CAP1__RETUNING_MODE_MASK 0x3
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#define ICFG_SDIOx_CAP1__RETUNING_MODE_SHIFT 11
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#define ICFG_SDIOx_CAP1__TUNE_SDR50_SHIFT 10
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#define ICFG_SDIOx_CAP1__TIME_RETUNE_MASK 0xf
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#define ICFG_SDIOx_CAP1__TIME_RETUNE_SHIFT 6
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#define ICFG_SDIOx_CAP1__DRIVER_D_SHIFT 5
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#define ICFG_SDIOx_CAP1__DRIVER_C_SHIFT 4
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#define ICFG_SDIOx_CAP1__DRIVER_A_SHIFT 3
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#define ICFG_SDIOx_CAP1__DDR50_SHIFT 2
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#define ICFG_SDIOx_CAP1__SDR104_SHIFT 1
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#define ICFG_SDIOx_CAP1__SDR50_SHIFT 0
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#ifdef USE_DDR
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#define SDIO_DMA 1
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#else
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#define SDIO_DMA 0
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#endif
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#define SDIO0_CAP0_CFG \
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(0x1 << ICFG_SDIOx_CAP0__SLOT_TYPE_SHIFT) \
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| (0x0 << ICFG_SDIOx_CAP0__INT_MODE_SHIFT) \
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| (0x0 << ICFG_SDIOx_CAP0__SYS_BUS_64BIT_SHIFT) \
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| (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_1P8V_SHIFT) \
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| (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_3P0V_SHIFT) \
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| (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_3P3V_SHIFT) \
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| (0x1 << ICFG_SDIOx_CAP0__SUSPEND_RESUME_SHIFT) \
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| (SDIO_DMA << ICFG_SDIOx_CAP0__SDMA_SHIFT) \
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| (SDIO_DMA << ICFG_SDIOx_CAP0__ADMA2_SHIFT) \
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| (0x1 << ICFG_SDIOx_CAP0__HIGH_SPEED_SHIFT) \
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| (0x1 << ICFG_SDIOx_CAP0__EXTENDED_MEDIA_SHIFT) \
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| (0x2 << ICFG_SDIOx_CAP0__MAX_BLOCK_LEN_SHIFT) \
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| (0xc8 << ICFG_SDIOx_CAP0__BASE_CLK_FREQ_SHIFT) \
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| (0x1 << ICFG_SDIOx_CAP0__TIMEOUT_UNIT_SHIFT) \
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| (0x30 << ICFG_SDIOx_CAP0__TIMEOUT_CLK_FREQ_SHIFT)
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#define SDIO0_CAP1_CFG \
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(0x1 << ICFG_SDIOx_CAP1__SPI_BLOCK_MODE_SHIFT)\
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| (0x1 << ICFG_SDIOx_CAP1__SPI_MODE_SHIFT)\
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| (0x0 << ICFG_SDIOx_CAP1__CLK_MULT_SHIFT)\
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| (0x2 << ICFG_SDIOx_CAP1__RETUNING_MODE_SHIFT)\
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| (0x1 << ICFG_SDIOx_CAP1__TUNE_SDR50_SHIFT)\
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| (0x0 << ICFG_SDIOx_CAP1__DRIVER_D_SHIFT)\
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| (0x0 << ICFG_SDIOx_CAP1__DRIVER_C_SHIFT)\
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| (0x1 << ICFG_SDIOx_CAP1__DRIVER_A_SHIFT)\
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| (0x1 << ICFG_SDIOx_CAP1__DDR50_SHIFT)\
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| (0x1 << ICFG_SDIOx_CAP1__SDR104_SHIFT)\
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| (0x1 << ICFG_SDIOx_CAP1__SDR50_SHIFT)
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#define SDIO1_CAP0_CFG \
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(0x0 << ICFG_SDIOx_CAP0__SLOT_TYPE_SHIFT) \
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| (0x0 << ICFG_SDIOx_CAP0__INT_MODE_SHIFT) \
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| (0x0 << ICFG_SDIOx_CAP0__SYS_BUS_64BIT_SHIFT) \
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| (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_1P8V_SHIFT) \
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| (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_3P0V_SHIFT) \
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| (0x1 << ICFG_SDIOx_CAP0__VOLTAGE_3P3V_SHIFT) \
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| (0x1 << ICFG_SDIOx_CAP0__SUSPEND_RESUME_SHIFT) \
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| (SDIO_DMA << ICFG_SDIOx_CAP0__SDMA_SHIFT) \
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| (SDIO_DMA << ICFG_SDIOx_CAP0__ADMA2_SHIFT) \
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| (0x1 << ICFG_SDIOx_CAP0__HIGH_SPEED_SHIFT) \
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| (0x1 << ICFG_SDIOx_CAP0__EXTENDED_MEDIA_SHIFT) \
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| (0x2 << ICFG_SDIOx_CAP0__MAX_BLOCK_LEN_SHIFT) \
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| (0xc8 << ICFG_SDIOx_CAP0__BASE_CLK_FREQ_SHIFT) \
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| (0x1 << ICFG_SDIOx_CAP0__TIMEOUT_UNIT_SHIFT) \
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| (0x30 << ICFG_SDIOx_CAP0__TIMEOUT_CLK_FREQ_SHIFT)
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#define SDIO1_CAP1_CFG \
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(0x1 << ICFG_SDIOx_CAP1__SPI_BLOCK_MODE_SHIFT)\
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| (0x1 << ICFG_SDIOx_CAP1__SPI_MODE_SHIFT)\
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| (0x0 << ICFG_SDIOx_CAP1__CLK_MULT_SHIFT)\
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| (0x2 << ICFG_SDIOx_CAP1__RETUNING_MODE_SHIFT)\
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| (0x1 << ICFG_SDIOx_CAP1__TUNE_SDR50_SHIFT)\
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| (0x0 << ICFG_SDIOx_CAP1__DRIVER_D_SHIFT)\
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| (0x0 << ICFG_SDIOx_CAP1__DRIVER_C_SHIFT)\
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| (0x1 << ICFG_SDIOx_CAP1__DRIVER_A_SHIFT)\
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| (0x1 << ICFG_SDIOx_CAP1__DDR50_SHIFT)\
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| (0x1 << ICFG_SDIOx_CAP1__SDR104_SHIFT)\
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| (0x1 << ICFG_SDIOx_CAP1__SDR50_SHIFT)
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#define PAD_SDIO_CLK 0x4
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#define PAD_SDIO_DATA0 0x8
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#define PAD_SDIO_DATA1 0xc
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#define PAD_SDIO_DATA2 0x10
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#define PAD_SDIO_DATA3 0x14
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#define PAD_SDIO_DATA4 0x18
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#define PAD_SDIO_DATA5 0x1c
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#define PAD_SDIO_DATA6 0x20
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#define PAD_SDIO_DATA7 0x24
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#define PAD_SDIO_CMD 0x28
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/* 12mA Drive strength*/
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#define PAD_SDIO_SELX (0x5 << 1)
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#define PAD_SDIO_SRC (1 << 0)
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#define PAD_SDIO_MASK (0xF << 0)
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#define PAD_SDIO_VALUE (PAD_SDIO_SELX | PAD_SDIO_SRC)
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/*
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* SDIO_PRESETVAL0
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*
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* Each 13 Bit filed consists:
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* drivestrength - 12:11
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* clkgensel - b10
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* sdkclkfreqsel - 9:0
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* Field Bit(s) Description
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* ============================================================
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* SDR25_PRESET 25:13 Preset Value for SDR25
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* SDR50_PRESET 12:0 Preset Value for SDR50
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*/
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#define SDIO_PRESETVAL0 0x01005001
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/*
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* SDIO_PRESETVAL1
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*
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* Each 13 Bit filed consists:
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* drivestrength - 12:11
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* clkgensel - b10
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* sdkclkfreqsel - 9:0
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* Field Bit(s) Description
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* ============================================================
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* SDR104_PRESET 25:13 Preset Value for SDR104
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* SDR12_PRESET 12:0 Preset Value for SDR12
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*/
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#define SDIO_PRESETVAL1 0x03000004
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/*
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* SDIO_PRESETVAL2
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*
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* Each 13 Bit filed consists:
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* drivestrength - 12:11
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* clkgensel - b10
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* sdkclkfreqsel - 9:0
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* Field Bit(s) Description
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* ============================================================
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* HIGH_SPEED_PRESET 25:13 Preset Value for High Speed
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* INIT_PRESET 12:0 Preset Value for Initialization
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*/
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#define SDIO_PRESETVAL2 0x010040FA
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/*
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* SDIO_PRESETVAL3
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*
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* Each 13 Bit filed consists:
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* drivestrength - 12:11
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* clkgensel - b10
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* sdkclkfreqsel - 9:0
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* Field Bit(s) Description
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* ============================================================
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* DDR50_PRESET 25:13 Preset Value for DDR50
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* DEFAULT_PRESET 12:0 Preset Value for Default Speed
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*/
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#define SDIO_PRESETVAL3 0x01004004
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/*
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* SDIO_PRESETVAL4
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*
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* Field Bit(s) Description
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* ============================================================
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* FORCE_USE_IP_TUNE_CLK 30 Force use IP clock
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* TUNING_COUNT 29:24 Tuning count
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* OVERRIDE_1P8V 23:16
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* OVERRIDE_3P3V 15:8
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* OVERRIDE_3P0V 7:0
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*/
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#define SDIO_PRESETVAL4 0x20010101
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#define SDIO_SID_SHIFT 5
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typedef struct {
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uintptr_t cfg_base;
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uintptr_t sid_base;
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uintptr_t io_ctrl_base;
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uintptr_t pad_base;
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} SDIO_CFG;
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void brcm_stingray_sdio_init(void);
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#endif /* SDIO_H */
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