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164 lines
3.9 KiB
164 lines
3.9 KiB
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <bl1/tbbr/tbbr_img_desc.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/pl011.h>
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#include <drivers/mmc.h>
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#include <drivers/synopsys/dw_mmc.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#include <hi6220.h>
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#include <hikey_def.h>
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#include <hikey_layout.h>
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#include "hikey_private.h"
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/* Data structure which holds the extents of the trusted RAM for BL1 */
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static meminfo_t bl1_tzram_layout;
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static console_t console;
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enum {
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BOOT_NORMAL = 0,
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BOOT_USB_DOWNLOAD,
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BOOT_UART_DOWNLOAD,
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};
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meminfo_t *bl1_plat_sec_mem_layout(void)
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{
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return &bl1_tzram_layout;
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}
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/*
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* Perform any BL1 specific platform actions.
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*/
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void bl1_early_platform_setup(void)
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{
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/* Initialize the console to provide early debug support */
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console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ,
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PL011_BAUDRATE, &console);
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/* Allow BL1 to see the whole Trusted RAM */
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bl1_tzram_layout.total_base = BL1_RW_BASE;
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bl1_tzram_layout.total_size = BL1_RW_SIZE;
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INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
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BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
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}
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/*
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* Perform the very early platform specific architecture setup here. At the
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* moment this only does basic initialization. Later architectural setup
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* (bl1_arch_setup()) does not do anything platform specific.
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*/
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void bl1_plat_arch_setup(void)
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{
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hikey_init_mmu_el3(bl1_tzram_layout.total_base,
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bl1_tzram_layout.total_size,
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BL1_RO_BASE,
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BL1_RO_LIMIT,
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BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END);
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}
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/*
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* Function which will perform any remaining platform-specific setup that can
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* occur after the MMU and data cache have been enabled.
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*/
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void bl1_platform_setup(void)
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{
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dw_mmc_params_t params;
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struct mmc_device_info info;
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assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) &&
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((SRAM_BASE + SRAM_SIZE) >=
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(HIKEY_BL1_MMC_DATA_BASE + HIKEY_BL1_MMC_DATA_SIZE)));
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hikey_sp804_init();
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hikey_gpio_init();
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hikey_pmussi_init();
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hikey_hi6553_init();
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hikey_rtc_init();
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hikey_mmc_pll_init();
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memset(¶ms, 0, sizeof(dw_mmc_params_t));
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params.reg_base = DWMMC0_BASE;
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params.desc_base = HIKEY_BL1_MMC_DESC_BASE;
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params.desc_size = 1 << 20;
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params.clk_rate = 24 * 1000 * 1000;
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params.bus_width = MMC_BUS_WIDTH_8;
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params.flags = MMC_FLAG_CMD23;
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info.mmc_dev_type = MMC_IS_EMMC;
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dw_mmc_init(¶ms, &info);
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hikey_io_setup();
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}
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/*
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* The following function checks if Firmware update is needed,
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* by checking if TOC in FIP image is valid or not.
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*/
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unsigned int bl1_plat_get_next_image_id(void)
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{
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int32_t boot_mode;
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unsigned int ret;
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boot_mode = mmio_read_32(ONCHIPROM_PARAM_BASE);
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switch (boot_mode) {
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case BOOT_USB_DOWNLOAD:
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case BOOT_UART_DOWNLOAD:
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ret = NS_BL1U_IMAGE_ID;
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break;
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default:
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WARN("Invalid boot mode is found:%d\n", boot_mode);
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panic();
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}
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return ret;
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}
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image_desc_t *bl1_plat_get_image_desc(unsigned int image_id)
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{
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unsigned int index = 0;
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while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) {
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if (bl1_tbbr_image_descs[index].image_id == image_id)
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return &bl1_tbbr_image_descs[index];
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index++;
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}
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return NULL;
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}
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void bl1_plat_set_ep_info(unsigned int image_id,
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entry_point_info_t *ep_info)
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{
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uint64_t data = 0;
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if (image_id == BL2_IMAGE_ID)
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panic();
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inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE);
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__asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data));
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do {
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data |= 3 << 20;
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__asm__ volatile ("msr cpacr_el1, %0" : : "r"(data));
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__asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data));
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} while ((data & (3 << 20)) != (3 << 20));
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INFO("cpacr_el1:0x%llx\n", data);
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ep_info->args.arg0 = 0xffff & read_mpidr();
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ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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}
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