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289 lines
7.5 KiB
289 lines
7.5 KiB
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/cci.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/sp804_delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <hi6220.h>
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#include <hikey_def.h>
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#include <hisi_ipc.h>
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#include <hisi_pwrc.h>
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#include <hisi_sram_map.h>
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#define CORE_PWR_STATE(state) \
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((state)->pwr_domain_state[MPIDR_AFFLVL0])
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#define CLUSTER_PWR_STATE(state) \
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((state)->pwr_domain_state[MPIDR_AFFLVL1])
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#define SYSTEM_PWR_STATE(state) \
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((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
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static uintptr_t hikey_sec_entrypoint;
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static int hikey_pwr_domain_on(u_register_t mpidr)
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{
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int cpu, cluster;
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int curr_cluster;
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cluster = MPIDR_AFFLVL1_VAL(mpidr);
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cpu = MPIDR_AFFLVL0_VAL(mpidr);
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curr_cluster = MPIDR_AFFLVL1_VAL(read_mpidr());
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if (cluster != curr_cluster)
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hisi_ipc_cluster_on(cpu, cluster);
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hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint);
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hisi_pwrc_enable_debug(cpu, cluster);
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hisi_ipc_cpu_on(cpu, cluster);
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return 0;
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}
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static void hikey_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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unsigned long mpidr;
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int cpu, cluster;
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mpidr = read_mpidr();
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cluster = MPIDR_AFFLVL1_VAL(mpidr);
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cpu = MPIDR_AFFLVL0_VAL(mpidr);
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/*
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* Enable CCI coherency for this cluster.
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* No need for locks as no other cpu is active at the moment.
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*/
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
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/* Zero the jump address in the mailbox for this cpu */
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hisi_pwrc_set_core_bx_addr(cpu, cluster, 0);
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/* Program the GIC per-cpu distributor or re-distributor interface */
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gicv2_pcpu_distif_init();
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/* Enable the GIC cpu interface */
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gicv2_cpuif_enable();
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}
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void hikey_pwr_domain_off(const psci_power_state_t *target_state)
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{
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unsigned long mpidr;
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int cpu, cluster;
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mpidr = read_mpidr();
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cluster = MPIDR_AFFLVL1_VAL(mpidr);
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cpu = MPIDR_AFFLVL0_VAL(mpidr);
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gicv2_cpuif_disable();
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hisi_ipc_cpu_off(cpu, cluster);
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE);
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cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
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hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE);
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hisi_ipc_cluster_off(cpu, cluster);
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}
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}
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static void hikey_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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u_register_t mpidr = read_mpidr_el1();
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unsigned int cpu = mpidr & MPIDR_CPU_MASK;
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unsigned int cluster =
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(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
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if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
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return;
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if (CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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/* Program the jump address for the target cpu */
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hisi_pwrc_set_core_bx_addr(cpu, cluster, hikey_sec_entrypoint);
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gicv2_cpuif_disable();
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if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
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hisi_ipc_cpu_suspend(cpu, cluster);
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}
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/* Perform the common cluster specific operations */
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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hisi_ipc_spin_lock(HISI_IPC_SEM_CPUIDLE);
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cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
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hisi_ipc_spin_unlock(HISI_IPC_SEM_CPUIDLE);
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if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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hisi_pwrc_set_cluster_wfi(1);
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hisi_pwrc_set_cluster_wfi(0);
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hisi_ipc_psci_system_off();
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} else
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hisi_ipc_cluster_suspend(cpu, cluster);
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}
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}
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static void hikey_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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unsigned long mpidr;
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unsigned int cluster, cpu;
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/* Nothing to be done on waking up from retention from CPU level */
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if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
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return;
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/* Get the mpidr for this cpu */
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mpidr = read_mpidr_el1();
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cluster = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFF1_SHIFT;
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cpu = mpidr & MPIDR_CPU_MASK;
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/* Enable CCI coherency for cluster */
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
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hisi_pwrc_set_core_bx_addr(cpu, cluster, 0);
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if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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} else {
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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}
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static void hikey_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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int i;
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for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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}
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static void __dead2 hikey_system_off(void)
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{
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NOTICE("%s: off system\n", __func__);
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/* Pull down GPIO_0_0 to trigger PMIC shutdown */
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mmio_write_32(0xF8001810, 0x2); /* Pinmux */
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mmio_write_8(0xF8011400, 1); /* Pin direction */
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mmio_write_8(0xF8011004, 0); /* Pin output value */
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/* Wait for 2s to power off system by PMIC */
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sp804_timer_init(SP804_TIMER0_BASE, 10, 192);
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mdelay(2000);
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/*
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* PMIC shutdown depends on two conditions: GPIO_0_0 (PWR_HOLD) low,
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* and VBUS_DET < 3.6V. For HiKey, VBUS_DET is connected to VDD_4V2
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* through Jumper 1-2. So, to complete shutdown, user needs to manually
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* remove Jumper 1-2.
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*/
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NOTICE("+------------------------------------------+\n");
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NOTICE("| IMPORTANT: Remove Jumper 1-2 to shutdown |\n");
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NOTICE("| DANGER: SoC is still burning. DANGER! |\n");
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NOTICE("| Board will be reboot to avoid overheat |\n");
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NOTICE("+------------------------------------------+\n");
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/* Send the system reset request */
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mmio_write_32(AO_SC_SYS_STAT0, 0x48698284);
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wfi();
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panic();
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}
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static void __dead2 hikey_system_reset(void)
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{
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/* Send the system reset request */
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mmio_write_32(AO_SC_SYS_STAT0, 0x48698284);
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isb();
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dsb();
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wfi();
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panic();
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}
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int hikey_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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int pstate = psci_get_pstate_type(power_state);
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int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
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int i;
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assert(req_state);
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if (pwr_lvl > PLAT_MAX_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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/* Sanity check the requested state */
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if (pstate == PSTATE_TYPE_STANDBY) {
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/*
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* It's possible to enter standby only on power level 0
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* Ignore any other power level.
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*/
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if (pwr_lvl != MPIDR_AFFLVL0)
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return PSCI_E_INVALID_PARAMS;
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req_state->pwr_domain_state[MPIDR_AFFLVL0] =
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PLAT_MAX_RET_STATE;
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} else {
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for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++)
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req_state->pwr_domain_state[i] =
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PLAT_MAX_OFF_STATE;
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}
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/*
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* We expect the 'state id' to be zero.
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*/
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if (psci_get_pstate_id(power_state))
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return PSCI_E_INVALID_PARAMS;
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return PSCI_E_SUCCESS;
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}
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static int hikey_validate_ns_entrypoint(uintptr_t entrypoint)
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{
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/*
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* Check if the non secure entrypoint lies within the non
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* secure DRAM.
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*/
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if ((entrypoint > DDR_BASE) && (entrypoint < (DDR_BASE + DDR_SIZE)))
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return PSCI_E_SUCCESS;
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return PSCI_E_INVALID_ADDRESS;
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}
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static const plat_psci_ops_t hikey_psci_ops = {
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.cpu_standby = NULL,
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.pwr_domain_on = hikey_pwr_domain_on,
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.pwr_domain_on_finish = hikey_pwr_domain_on_finish,
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.pwr_domain_off = hikey_pwr_domain_off,
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.pwr_domain_suspend = hikey_pwr_domain_suspend,
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.pwr_domain_suspend_finish = hikey_pwr_domain_suspend_finish,
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.system_off = hikey_system_off,
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.system_reset = hikey_system_reset,
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.validate_power_state = hikey_validate_power_state,
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.validate_ns_entrypoint = hikey_validate_ns_entrypoint,
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.get_sys_suspend_power_state = hikey_get_sys_suspend_power_state,
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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hikey_sec_entrypoint = sec_entrypoint;
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/*
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* Initialize PSCI ops struct
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*/
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*psci_ops = &hikey_psci_ops;
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return 0;
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}
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