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136 lines
3.5 KiB
136 lines
3.5 KiB
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stddef.h>
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#include <string.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <bl31/bl31.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <cortex_a53.h>
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#include <drivers/arm/pl011.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#include "hi3798cv200.h"
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#include "plat_private.h"
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#define TZPC_SEC_ATTR_CTRL_VALUE (0x9DB98D45)
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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static console_t console;
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static void hisi_tzpc_sec_init(void)
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{
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mmio_write_32(HISI_TZPC_SEC_ATTR_CTRL, TZPC_SEC_ATTR_CTRL_VALUE);
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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assert(sec_state_is_valid(type));
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next_image_info = (type == NON_SECURE)
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? &bl33_image_ep_info : &bl32_image_ep_info;
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/*
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* None of the images on the ARM development platforms can have 0x0
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* as the entrypoint
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*/
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if (next_image_info->pc)
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return next_image_info;
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else
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return NULL;
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}
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/*******************************************************************************
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* Perform any BL31 early platform setup common to ARM standard platforms.
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* Here is an opportunity to copy parameters passed by the calling EL (S-EL1
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* in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be
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* done before the MMU is initialized so that the memory layout can be used
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* while creating page tables. BL2 has flushed this information to memory, so
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* we are guaranteed to pick up good data.
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******************************************************************************/
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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void *from_bl2;
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from_bl2 = (void *) arg0;
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console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ,
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PL011_BAUDRATE, &console);
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/* Init console for crash report */
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plat_crash_console_init();
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/*
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* Check params passed from BL2 should not be NULL,
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*/
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bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
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assert(params_from_bl2 != NULL);
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assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
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assert(params_from_bl2->h.version >= VERSION_2);
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bl_params_node_t *bl_params = params_from_bl2->head;
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/*
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* Copy BL33 and BL32 (if present), entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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while (bl_params) {
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if (bl_params->image_id == BL32_IMAGE_ID)
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bl32_image_ep_info = *bl_params->ep_info;
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if (bl_params->image_id == BL33_IMAGE_ID)
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bl33_image_ep_info = *bl_params->ep_info;
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bl_params = bl_params->next_params_info;
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}
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if (bl33_image_ep_info.pc == 0)
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panic();
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}
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void bl31_platform_setup(void)
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{
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/* Init arch timer */
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generic_delay_timer_init();
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/* Init GIC distributor and CPU interface */
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poplar_gic_driver_init();
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poplar_gic_init();
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/* Init security properties of IP blocks */
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hisi_tzpc_sec_init();
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}
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void bl31_plat_runtime_setup(void)
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{
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/* do nothing */
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}
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void bl31_plat_arch_setup(void)
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{
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plat_configure_mmu_el3(BL31_BASE,
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(BL31_LIMIT - BL31_BASE),
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BL_CODE_BASE,
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BL_CODE_END,
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BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END);
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INFO("Boot BL33 from 0x%lx for %llu Bytes\n",
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bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2);
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}
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