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414 lines
12 KiB
414 lines
12 KiB
/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <context.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/cci.h>
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#include <drivers/console.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <plat/common/platform.h>
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#include <imx8qm_pads.h>
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#include <imx8_iomux.h>
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#include <imx8_lpuart.h>
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#include <plat_imx8.h>
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#include <sci/sci.h>
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#include <sec_rsrc.h>
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static const unsigned long BL31_COHERENT_RAM_START = BL_COHERENT_RAM_BASE;
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static const unsigned long BL31_COHERENT_RAM_END = BL_COHERENT_RAM_END;
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static const unsigned long BL31_RO_START = BL_CODE_BASE;
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static const unsigned long BL31_RO_END = BL_CODE_END;
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static const unsigned long BL31_RW_END = BL_END;
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IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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#define UART_PAD_CTRL (PADRING_IFMUX_EN_MASK | PADRING_GP_EN_MASK | \
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(SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
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(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
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(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
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(SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT))
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#if defined(IMX_USE_UART0)
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#define IMX_RES_UART SC_R_UART_0
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#define IMX_PAD_UART_RX SC_P_UART0_RX
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#define IMX_PAD_UART_TX SC_P_UART0_TX
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#define IMX_PAD_UART_RTS_B SC_P_UART0_RTS_B
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#define IMX_PAD_UART_CTS_B SC_P_UART0_CTS_B
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#elif defined(IMX_USE_UART1)
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#define IMX_RES_UART SC_R_UART_1
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#define IMX_PAD_UART_RX SC_P_UART1_RX
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#define IMX_PAD_UART_TX SC_P_UART1_TX
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#define IMX_PAD_UART_RTS_B SC_P_UART1_RTS_B
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#define IMX_PAD_UART_CTS_B SC_P_UART1_CTS_B
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#else
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#error "Provide proper UART number in IMX_DEBUG_UART"
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#endif
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const static int imx8qm_cci_map[] = {
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CLUSTER0_CCI_SLVAE_IFACE,
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CLUSTER1_CCI_SLVAE_IFACE
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};
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static const mmap_region_t imx_mmap[] = {
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MAP_REGION_FLAT(IMX_REG_BASE, IMX_REG_SIZE, MT_DEVICE | MT_RW),
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{0}
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};
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static uint32_t get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned long mode;
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uint32_t spsr;
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/* figure out what mode we enter the non-secure world */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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#if DEBUG_CONSOLE_A53
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static void lpuart32_serial_setbrg(unsigned int base, int baudrate)
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{
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unsigned int sbr, osr, baud_diff, tmp_osr, tmp_sbr;
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unsigned int diff1, diff2, tmp, rate;
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if (baudrate == 0)
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panic();
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sc_pm_get_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate);
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baud_diff = baudrate;
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osr = 0;
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sbr = 0;
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for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
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tmp_sbr = (rate / (baudrate * tmp_osr));
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if (tmp_sbr == 0)
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tmp_sbr = 1;
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/* calculate difference in actual baud w/ current values */
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diff1 = rate / (tmp_osr * tmp_sbr) - baudrate;
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diff2 = rate / (tmp_osr * (tmp_sbr + 1));
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/* select best values between sbr and sbr+1 */
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if (diff1 > (baudrate - diff2)) {
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diff1 = baudrate - diff2;
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tmp_sbr++;
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}
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if (diff1 <= baud_diff) {
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baud_diff = diff1;
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osr = tmp_osr;
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sbr = tmp_sbr;
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}
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}
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tmp = mmio_read_32(IMX_BOOT_UART_BASE + BAUD);
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if ((osr > 3) && (osr < 8))
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tmp |= LPUART_BAUD_BOTHEDGE_MASK;
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tmp &= ~LPUART_BAUD_OSR_MASK;
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tmp |= LPUART_BAUD_OSR(osr - 1);
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tmp &= ~LPUART_BAUD_SBR_MASK;
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tmp |= LPUART_BAUD_SBR(sbr);
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/* explicitly disable 10 bit mode & set 1 stop bit */
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tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
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mmio_write_32(IMX_BOOT_UART_BASE + BAUD, tmp);
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}
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static int lpuart32_serial_init(unsigned int base)
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{
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unsigned int tmp;
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/* disable TX & RX before enabling clocks */
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tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL);
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tmp &= ~(CTRL_TE | CTRL_RE);
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mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp);
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mmio_write_32(IMX_BOOT_UART_BASE + MODIR, 0);
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mmio_write_32(IMX_BOOT_UART_BASE + FIFO, ~(FIFO_TXFE | FIFO_RXFE));
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mmio_write_32(IMX_BOOT_UART_BASE + MATCH, 0);
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/* provide data bits, parity, stop bit, etc */
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lpuart32_serial_setbrg(base, IMX_BOOT_UART_BAUDRATE);
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/* eight data bits no parity bit */
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tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL);
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tmp &= ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK);
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mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp);
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mmio_write_32(IMX_BOOT_UART_BASE + CTRL, CTRL_RE | CTRL_TE);
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mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55);
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mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55);
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mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x0A);
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return 0;
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}
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#endif
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void mx8_partition_resources(void)
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{
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sc_rm_pt_t secure_part, os_part;
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sc_rm_mr_t mr, mr_record = 64;
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sc_faddr_t start, end;
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bool owned, owned2;
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sc_err_t err;
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int i;
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err = sc_rm_get_partition(ipc_handle, &secure_part);
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err = sc_rm_partition_alloc(ipc_handle, &os_part, false, false,
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false, false, false);
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err = sc_rm_set_parent(ipc_handle, os_part, secure_part);
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/* set secure resources to NOT-movable */
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for (i = 0; i < ARRAY_SIZE(secure_rsrcs); i++) {
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err = sc_rm_set_resource_movable(ipc_handle, secure_rsrcs[i],
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secure_rsrcs[i], false);
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if (err)
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ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
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secure_rsrcs[i], err);
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}
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owned = sc_rm_is_resource_owned(ipc_handle, SC_R_M4_0_PID0);
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if (owned) {
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err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_0_PID0,
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SC_R_M4_0_PID0, false);
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if (err)
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ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
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SC_R_M4_0_PID0, err);
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}
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owned2 = sc_rm_is_resource_owned(ipc_handle, SC_R_M4_1_PID0);
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if (owned2) {
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err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_1_PID0,
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SC_R_M4_1_PID0, false);
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if (err)
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ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
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SC_R_M4_1_PID0, err);
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}
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/* move all movable resources and pins to non-secure partition */
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err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true);
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if (err)
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ERROR("sc_rm_move_all: %u\n", err);
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/* iterate through peripherals to give NS OS part access */
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for (i = 0; i < ARRAY_SIZE(ns_access_allowed); i++) {
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err = sc_rm_set_peripheral_permissions(ipc_handle, ns_access_allowed[i],
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os_part, SC_RM_PERM_FULL);
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if (err)
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ERROR("sc_rm_set_peripheral_permissions: rsrc %u, \
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ret %u\n", ns_access_allowed[i], err);
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}
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if (owned) {
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err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_0_PID0,
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SC_R_M4_0_PID0, true);
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if (err)
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ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
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SC_R_M4_0_PID0, err);
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err = sc_rm_assign_resource(ipc_handle, os_part, SC_R_M4_0_PID0);
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if (err)
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ERROR("sc_rm_assign_resource: rsrc %u, ret %u\n",
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SC_R_M4_0_PID0, err);
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}
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if (owned2) {
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err = sc_rm_set_resource_movable(ipc_handle, SC_R_M4_1_PID0,
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SC_R_M4_1_PID0, true);
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if (err)
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ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n",
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SC_R_M4_1_PID0, err);
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err = sc_rm_assign_resource(ipc_handle, os_part, SC_R_M4_1_PID0);
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if (err)
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ERROR("sc_rm_assign_resource: rsrc %u, ret %u\n",
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SC_R_M4_1_PID0, err);
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}
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/*
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* sc_rm_set_peripheral_permissions
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* sc_rm_set_memreg_permissions
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* sc_rm_set_pin_movable
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*/
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for (mr = 0; mr < 64; mr++) {
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owned = sc_rm_is_memreg_owned(ipc_handle, mr);
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if (owned) {
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err = sc_rm_get_memreg_info(ipc_handle, mr, &start, &end);
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if (err)
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ERROR("Memreg get info failed, %u\n", mr);
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NOTICE("Memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
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if (BL31_BASE >= start && (BL31_LIMIT - 1) <= end) {
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mr_record = mr; /* Record the mr for ATF running */
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} else {
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err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
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if (err)
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ERROR("Memreg assign failed, 0x%llx -- 0x%llx, \
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err %d\n", start, end, err);
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}
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}
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}
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if (mr_record != 64) {
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err = sc_rm_get_memreg_info(ipc_handle, mr_record, &start, &end);
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if (err)
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ERROR("Memreg get info failed, %u\n", mr_record);
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if ((BL31_LIMIT - 1) < end) {
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err = sc_rm_memreg_alloc(ipc_handle, &mr, BL31_LIMIT, end);
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if (err)
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ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n",
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(sc_faddr_t)BL31_LIMIT, end);
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err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
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if (err)
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ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n",
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(sc_faddr_t)BL31_LIMIT, end);
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}
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if (start < (BL31_BASE - 1)) {
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err = sc_rm_memreg_alloc(ipc_handle, &mr, start, BL31_BASE - 1);
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if (err)
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ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n",
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start, (sc_faddr_t)BL31_BASE - 1);
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err = sc_rm_assign_memreg(ipc_handle, os_part, mr);
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if (err)
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ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n",
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start, (sc_faddr_t)BL31_BASE - 1);
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}
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}
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if (err)
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NOTICE("Partitioning Failed\n");
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else
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NOTICE("Non-secure Partitioning Succeeded\n");
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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#if DEBUG_CONSOLE
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static console_t console;
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#endif
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if (sc_ipc_open(&ipc_handle, SC_IPC_BASE) != SC_ERR_NONE)
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panic();
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#if DEBUG_CONSOLE_A53
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sc_pm_set_resource_power_mode(ipc_handle, IMX_RES_UART,
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SC_PM_PW_MODE_ON);
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sc_pm_clock_rate_t rate = 80000000;
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sc_pm_set_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate);
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sc_pm_clock_enable(ipc_handle, IMX_RES_UART, 2, true, false);
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/* configure UART pads */
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sc_pad_set(ipc_handle, IMX_PAD_UART_RX, UART_PAD_CTRL);
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sc_pad_set(ipc_handle, IMX_PAD_UART_TX, UART_PAD_CTRL);
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sc_pad_set(ipc_handle, IMX_PAD_UART_RTS_B, UART_PAD_CTRL);
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sc_pad_set(ipc_handle, IMX_PAD_UART_CTS_B, UART_PAD_CTRL);
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lpuart32_serial_init(IMX_BOOT_UART_BASE);
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#endif
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#if DEBUG_CONSOLE
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console_lpuart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
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IMX_CONSOLE_BAUDRATE, &console);
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#endif
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/* turn on MU1 for non-secure OS/Hypervisor */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON);
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/* Turn on GPT_0's power & clock for non-secure OS/Hypervisor */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON);
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sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0);
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mmio_write_32(IMX_GPT_LPCG_BASE, mmio_read_32(IMX_GPT_LPCG_BASE) | (1 << 25));
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/*
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* create new partition for non-secure OS/Hypervisor
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* uses global structs defined in sec_rsrc.h
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*/
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mx8_partition_resources();
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bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
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bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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/* init the first cluster's cci slave interface */
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cci_init(PLAT_CCI_BASE, imx8qm_cci_map, PLATFORM_CLUSTER_COUNT);
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
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}
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void bl31_plat_arch_setup(void)
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{
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unsigned long ro_start = BL31_RO_START;
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unsigned long ro_size = BL31_RO_END - BL31_RO_START;
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unsigned long rw_start = BL31_RW_START;
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unsigned long rw_size = BL31_RW_END - BL31_RW_START;
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#if USE_COHERENT_MEM
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unsigned long coh_start = BL31_COHERENT_RAM_START;
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unsigned long coh_size = BL31_COHERENT_RAM_END - BL31_COHERENT_RAM_START;
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#endif
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mmap_add_region(ro_start, ro_start, ro_size,
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MT_RO | MT_MEMORY | MT_SECURE);
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mmap_add_region(rw_start, rw_start, rw_size,
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MT_RW | MT_MEMORY | MT_SECURE);
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mmap_add(imx_mmap);
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#if USE_COHERENT_MEM
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mmap_add_region(coh_start, coh_start, coh_size,
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MT_DEVICE | MT_RW | MT_SECURE);
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#endif
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/* setup xlat table */
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init_xlat_tables();
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/* enable the MMU */
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enable_mmu_el3(0);
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}
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void bl31_platform_setup(void)
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{
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plat_gic_driver_init();
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plat_gic_init();
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
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{
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if (type == NON_SECURE)
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return &bl33_image_ep_info;
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if (type == SECURE)
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return &bl32_image_ep_info;
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return NULL;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return COUNTER_FREQUENCY;
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}
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void bl31_plat_runtime_setup(void)
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{
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return;
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}
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