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141 lines
4.8 KiB
141 lines
4.8 KiB
/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT8173_DEF_H
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#define MT8173_DEF_H
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#if RESET_TO_BL31
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#error "MT8173 is incompatible with RESET_TO_BL31!"
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#endif
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#define MT8173_PRIMARY_CPU 0x0
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/* Register base address */
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#define IO_PHYS (0x10000000)
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#define INFRACFG_AO_BASE (IO_PHYS + 0x1000)
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#define SRAMROM_SEC_BASE (IO_PHYS + 0x1800)
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#define PERI_CON_BASE (IO_PHYS + 0x3000)
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#define GPIO_BASE (IO_PHYS + 0x5000)
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#define SPM_BASE (IO_PHYS + 0x6000)
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#define RGU_BASE (IO_PHYS + 0x7000)
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#define PMIC_WRAP_BASE (IO_PHYS + 0xD000)
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#define DEVAPC0_BASE (IO_PHYS + 0xE000)
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#define MCUCFG_BASE (IO_PHYS + 0x200000)
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#define APMIXED_BASE (IO_PHYS + 0x209000)
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#define TRNG_BASE (IO_PHYS + 0x20F000)
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#define CRYPT_BASE (IO_PHYS + 0x210000)
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#define MT_GIC_BASE (IO_PHYS + 0x220000)
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#define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000)
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/* Aggregate of all devices in the first GB */
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#define MTK_DEV_RNG0_BASE IO_PHYS
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#define MTK_DEV_RNG0_SIZE 0x400000
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#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000)
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#define MTK_DEV_RNG1_SIZE 0x4000000
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/* SRAMROM related registers */
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#define SRAMROM_SEC_CTRL (SRAMROM_SEC_BASE + 0x4)
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#define SRAMROM_SEC_ADDR (SRAMROM_SEC_BASE + 0x8)
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/* DEVAPC0 related registers */
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#define DEVAPC0_MAS_SEC_0 (DEVAPC0_BASE + 0x500)
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#define DEVAPC0_APC_CON (DEVAPC0_BASE + 0xF00)
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define MT8173_UART0_BASE (IO_PHYS + 0x01002000)
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#define MT8173_UART1_BASE (IO_PHYS + 0x01003000)
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#define MT8173_UART2_BASE (IO_PHYS + 0x01004000)
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#define MT8173_UART3_BASE (IO_PHYS + 0x01005000)
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#define MT8173_BAUDRATE (115200)
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#define MT8173_UART_CLOCK (26000000)
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/*******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define SYS_COUNTER_FREQ_IN_TICKS 13000000
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/*******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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/* Base MTK_platform compatible GIC memory map */
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#define BASE_GICD_BASE (MT_GIC_BASE + 0x1000)
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#define BASE_GICC_BASE (MT_GIC_BASE + 0x2000)
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#define BASE_GICR_BASE 0 /* no GICR in GIC-400 */
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#define BASE_GICH_BASE (MT_GIC_BASE + 0x4000)
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#define BASE_GICV_BASE (MT_GIC_BASE + 0x6000)
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#define INT_POL_CTL0 0x10200620
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#define GIC_PRIVATE_SIGNALS (32)
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/*******************************************************************************
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* CCI-400 related constants
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******************************************************************************/
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#define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4
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#define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3
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/* FIQ platform related define */
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#define MT_IRQ_SEC_SGI_0 8
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#define MT_IRQ_SEC_SGI_1 9
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#define MT_IRQ_SEC_SGI_2 10
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#define MT_IRQ_SEC_SGI_3 11
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#define MT_IRQ_SEC_SGI_4 12
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#define MT_IRQ_SEC_SGI_5 13
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#define MT_IRQ_SEC_SGI_6 14
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#define MT_IRQ_SEC_SGI_7 15
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/*
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* Macros for local power states in MTK platforms encoded by State-ID field
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* within the power-state parameter.
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*/
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/* Local power state for power domains in Run state. */
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#define MTK_LOCAL_STATE_RUN 0
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/* Local power state for retention. Valid only for CPU power domains */
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#define MTK_LOCAL_STATE_RET 1
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/* Local power state for OFF/power-down. Valid for CPU and cluster power
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* domains
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*/
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#define MTK_LOCAL_STATE_OFF 2
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#if PSCI_EXTENDED_STATE_ID
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/*
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* Macros used to parse state information from State-ID if it is using the
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* recommended encoding for State-ID.
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*/
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#define MTK_LOCAL_PSTATE_WIDTH 4
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#define MTK_LOCAL_PSTATE_MASK ((1 << MTK_LOCAL_PSTATE_WIDTH) - 1)
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/* Macros to construct the composite power state */
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/* Make composite power state parameter till power level 0 */
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#define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
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(((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
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#else
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#define mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
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(((lvl0_state) << PSTATE_ID_SHIFT) | \
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((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
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((type) << PSTATE_TYPE_SHIFT))
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#endif /* __PSCI_EXTENDED_STATE_ID__ */
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/* Make composite power state parameter till power level 1 */
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#define mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
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(((lvl1_state) << MTK_LOCAL_PSTATE_WIDTH) | \
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mtk_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
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/* Make composite power state parameter till power level 2 */
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#define mtk_make_pwrstate_lvl2( \
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lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \
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(((lvl2_state) << (MTK_LOCAL_PSTATE_WIDTH * 2)) | \
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mtk_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
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#endif /* MT8173_DEF_H */
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