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311 lines
7.4 KiB
311 lines
7.4 KiB
/*
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* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/cci.h>
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#include <drivers/arm/gicv2.h>
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#include <lib/bakery_lock.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#include "iic_dvfs.h"
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#include "platform_def.h"
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#include "pwrc.h"
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#include "rcar_def.h"
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#include "rcar_private.h"
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#if RCAR_GEN3_ULCB
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#include "ulcb_cpld.h"
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#endif /* RCAR_GEN3_ULCB */
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#define DVFS_SET_VID_0V (0x00)
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#define P_ALL_OFF (0x80)
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#define KEEPON_DDR1C (0x08)
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#define KEEPON_DDR0C (0x04)
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#define KEEPON_DDR1 (0x02)
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#define KEEPON_DDR0 (0x01)
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#define SYSTEM_PWR_STATE(s) ((s)->pwr_domain_state[PLAT_MAX_PWR_LVL])
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#define CLUSTER_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL1])
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#define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0])
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extern void rcar_pwrc_restore_generic_timer(uint64_t *stack);
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extern void plat_rcar_gic_driver_init(void);
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extern void plat_rcar_gic_init(void);
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extern u_register_t rcar_boot_mpidr;
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static uintptr_t rcar_sec_entrypoint;
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static void rcar_program_mailbox(uint64_t mpidr, uint64_t address)
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{
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mailbox_t *rcar_mboxes = (mailbox_t *) MBOX_BASE;
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uint64_t linear_id = plat_core_pos_by_mpidr(mpidr);
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unsigned long range;
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rcar_mboxes[linear_id].value = address;
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range = (unsigned long)&rcar_mboxes[linear_id];
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flush_dcache_range(range, sizeof(range));
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}
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static void rcar_cpu_standby(plat_local_state_t cpu_state)
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{
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u_register_t scr_el3 = read_scr_el3();
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write_scr_el3(scr_el3 | SCR_IRQ_BIT);
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dsb();
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wfi();
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write_scr_el3(scr_el3);
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}
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static int rcar_pwr_domain_on(u_register_t mpidr)
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{
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rcar_program_mailbox(mpidr, rcar_sec_entrypoint);
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rcar_pwrc_cpuon(mpidr);
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return PSCI_E_SUCCESS;
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}
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static void rcar_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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uint32_t cluster_type = rcar_pwrc_get_cluster();
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unsigned long mpidr = read_mpidr_el1();
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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if (cluster_type == RCAR_CLUSTER_A53A57)
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plat_cci_enable();
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rcar_pwrc_disable_interrupt_wakeup(mpidr);
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rcar_program_mailbox(mpidr, 0);
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gicv2_cpuif_enable();
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gicv2_pcpu_distif_init();
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}
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static void rcar_pwr_domain_off(const psci_power_state_t *target_state)
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{
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#if RCAR_LSI != RCAR_D3
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uint32_t cluster_type = rcar_pwrc_get_cluster();
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#endif
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unsigned long mpidr = read_mpidr_el1();
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gicv2_cpuif_disable();
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rcar_pwrc_cpuoff(mpidr);
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#if RCAR_LSI != RCAR_D3
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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if (cluster_type == RCAR_CLUSTER_A53A57)
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plat_cci_disable();
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rcar_pwrc_clusteroff(mpidr);
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}
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#endif
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}
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static void rcar_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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uint32_t cluster_type = rcar_pwrc_get_cluster();
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unsigned long mpidr = read_mpidr_el1();
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if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
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return;
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rcar_program_mailbox(mpidr, rcar_sec_entrypoint);
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rcar_pwrc_enable_interrupt_wakeup(mpidr);
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gicv2_cpuif_disable();
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rcar_pwrc_cpuoff(mpidr);
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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if (cluster_type == RCAR_CLUSTER_A53A57)
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plat_cci_disable();
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rcar_pwrc_clusteroff(mpidr);
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}
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#if RCAR_SYSTEM_SUSPEND
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if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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rcar_pwrc_suspend_to_ram();
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#endif
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}
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static void rcar_pwr_domain_suspend_finish(const psci_power_state_t
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*target_state)
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{
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uint32_t cluster_type = rcar_pwrc_get_cluster();
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if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
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goto finish;
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plat_rcar_gic_driver_init();
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plat_rcar_gic_init();
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if (cluster_type == RCAR_CLUSTER_A53A57)
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plat_cci_init();
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rcar_pwrc_restore_timer_state();
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rcar_pwrc_setup();
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rcar_pwrc_code_copy_to_system_ram();
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#if RCAR_SYSTEM_SUSPEND
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rcar_pwrc_init_suspend_to_ram();
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#endif
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finish:
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rcar_pwr_domain_on_finish(target_state);
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}
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static void __dead2 rcar_system_off(void)
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{
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#if PMIC_ROHM_BD9571
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#if PMIC_LEVEL_MODE
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if (rcar_iic_dvfs_send(PMIC, DVFS_SET_VID, DVFS_SET_VID_0V))
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ERROR("BL3-1:Failed the SYSTEM-OFF.\n");
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#else
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if (rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, P_ALL_OFF))
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ERROR("BL3-1:Failed the SYSTEM-RESET.\n");
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#endif
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#else
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uint64_t cpu = read_mpidr_el1() & 0x0000ffff;
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int32_t rtn_on;
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rtn_on = rcar_pwrc_cpu_on_check(cpu);
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if (cpu == rcar_boot_mpidr)
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panic();
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if (rtn_on)
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panic();
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rcar_pwrc_cpuoff(cpu);
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rcar_pwrc_clusteroff(cpu);
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#endif /* PMIC_ROHM_BD9571 */
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wfi();
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ERROR("RCAR System Off: operation not handled.\n");
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panic();
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}
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static void __dead2 rcar_system_reset(void)
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{
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#if PMIC_ROHM_BD9571
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#if PMIC_LEVEL_MODE
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#if RCAR_SYSTEM_RESET_KEEPON_DDR
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uint8_t mode;
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int32_t error;
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error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, KEEP10_MAGIC);
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if (error) {
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ERROR("Failed send KEEP10 magic ret=%d\n", error);
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goto done;
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}
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error = rcar_iic_dvfs_receive(PMIC, BKUP_MODE_CNT, &mode);
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if (error) {
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ERROR("Failed receive BKUP_Mode_Cnt ret=%d\n", error);
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goto done;
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}
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mode |= KEEPON_DDR1C | KEEPON_DDR0C | KEEPON_DDR1 | KEEPON_DDR0;
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error = rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, mode);
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if (error) {
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ERROR("Failed send KEEPON_DDRx ret=%d\n", error);
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goto done;
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}
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rcar_pwrc_set_suspend_to_ram();
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done:
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#else
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if (rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, P_ALL_OFF))
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ERROR("BL3-1:Failed the SYSTEM-RESET.\n");
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#endif
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#else
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#if (RCAR_GEN3_ULCB == 1)
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rcar_cpld_reset_cpu();
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#endif
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#endif
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#else
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rcar_pwrc_system_reset();
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#endif
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wfi();
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ERROR("RCAR System Reset: operation not handled.\n");
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panic();
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}
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static int rcar_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
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unsigned int pstate = psci_get_pstate_type(power_state);
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uint32_t i;
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if (pstate == PSTATE_TYPE_STANDBY) {
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if (pwr_lvl != MPIDR_AFFLVL0)
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return PSCI_E_INVALID_PARAMS;
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req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
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} else {
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for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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}
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if (psci_get_pstate_id(power_state))
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return PSCI_E_INVALID_PARAMS;
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return PSCI_E_SUCCESS;
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}
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#if RCAR_SYSTEM_SUSPEND
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static void rcar_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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unsigned long mpidr = read_mpidr_el1() & 0x0000ffffU;
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int i;
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if (mpidr != rcar_boot_mpidr)
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goto deny;
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for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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return;
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deny:
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/* deny system suspend entry */
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req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSCI_LOCAL_STATE_RUN;
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for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE;
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}
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#endif
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static const plat_psci_ops_t rcar_plat_psci_ops = {
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.cpu_standby = rcar_cpu_standby,
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.pwr_domain_on = rcar_pwr_domain_on,
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.pwr_domain_off = rcar_pwr_domain_off,
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.pwr_domain_suspend = rcar_pwr_domain_suspend,
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.pwr_domain_on_finish = rcar_pwr_domain_on_finish,
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.pwr_domain_suspend_finish = rcar_pwr_domain_suspend_finish,
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.system_off = rcar_system_off,
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.system_reset = rcar_system_reset,
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.validate_power_state = rcar_validate_power_state,
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#if RCAR_SYSTEM_SUSPEND
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.get_sys_suspend_power_state = rcar_get_sys_suspend_power_state,
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#endif
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops)
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{
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*psci_ops = &rcar_plat_psci_ops;
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rcar_sec_entrypoint = sec_entrypoint;
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#if RCAR_SYSTEM_SUSPEND
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rcar_pwrc_init_suspend_to_ram();
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#endif
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return 0;
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}
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