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414 lines
12 KiB
414 lines
12 KiB
/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/console.h>
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#include <drivers/delay_timer.h>
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#include <lib/psci/psci.h>
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#include <plat_private.h>
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/* Macros to read the rk power domain state */
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#define RK_CORE_PWR_STATE(state) \
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((state)->pwr_domain_state[MPIDR_AFFLVL0])
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#define RK_CLUSTER_PWR_STATE(state) \
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((state)->pwr_domain_state[MPIDR_AFFLVL1])
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#define RK_SYSTEM_PWR_STATE(state) \
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((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
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static uintptr_t rockchip_sec_entrypoint;
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#pragma weak rockchip_soc_cores_pwr_dm_on
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#pragma weak rockchip_soc_hlvl_pwr_dm_off
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#pragma weak rockchip_soc_cores_pwr_dm_off
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#pragma weak rockchip_soc_sys_pwr_dm_suspend
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#pragma weak rockchip_soc_cores_pwr_dm_suspend
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#pragma weak rockchip_soc_hlvl_pwr_dm_suspend
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#pragma weak rockchip_soc_hlvl_pwr_dm_on_finish
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#pragma weak rockchip_soc_cores_pwr_dm_on_finish
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#pragma weak rockchip_soc_sys_pwr_dm_resume
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#pragma weak rockchip_soc_hlvl_pwr_dm_resume
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#pragma weak rockchip_soc_cores_pwr_dm_resume
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#pragma weak rockchip_soc_soft_reset
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#pragma weak rockchip_soc_system_off
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#pragma weak rockchip_soc_sys_pd_pwr_dn_wfi
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#pragma weak rockchip_soc_cores_pd_pwr_dn_wfi
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int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
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plat_local_state_t lvl_state)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_cores_pwr_dm_off(void)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_sys_pwr_dm_suspend(void)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_cores_pwr_dm_suspend(void)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl,
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plat_local_state_t lvl_state)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
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plat_local_state_t lvl_state)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_cores_pwr_dm_on_finish(void)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_sys_pwr_dm_resume(void)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl,
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plat_local_state_t lvl_state)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int rockchip_soc_cores_pwr_dm_resume(void)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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void __dead2 rockchip_soc_soft_reset(void)
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{
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while (1)
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;
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}
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void __dead2 rockchip_soc_system_off(void)
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{
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while (1)
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;
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}
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void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi(
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const psci_power_state_t *target_state)
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{
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psci_power_down_wfi();
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}
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void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void)
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{
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psci_power_down_wfi();
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}
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/*******************************************************************************
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* Rockchip standard platform handler called to check the validity of the power
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* state parameter.
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******************************************************************************/
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int rockchip_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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int pstate = psci_get_pstate_type(power_state);
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int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
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int i;
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assert(req_state);
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if (pwr_lvl > PLAT_MAX_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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/* Sanity check the requested state */
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if (pstate == PSTATE_TYPE_STANDBY) {
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/*
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* It's probably to enter standby only on power level 0
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* ignore any other power level.
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*/
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if (pwr_lvl != MPIDR_AFFLVL0)
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return PSCI_E_INVALID_PARAMS;
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req_state->pwr_domain_state[MPIDR_AFFLVL0] =
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PLAT_MAX_RET_STATE;
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} else {
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for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++)
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req_state->pwr_domain_state[i] =
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PLAT_MAX_OFF_STATE;
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for (i = (pwr_lvl + 1); i <= PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] =
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PLAT_MAX_RET_STATE;
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}
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/* We expect the 'state id' to be zero */
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if (psci_get_pstate_id(power_state))
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return PSCI_E_INVALID_PARAMS;
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return PSCI_E_SUCCESS;
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}
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void rockchip_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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int i;
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for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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}
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/*******************************************************************************
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* RockChip handler called when a CPU is about to enter standby.
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******************************************************************************/
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void rockchip_cpu_standby(plat_local_state_t cpu_state)
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{
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u_register_t scr;
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assert(cpu_state == PLAT_MAX_RET_STATE);
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scr = read_scr_el3();
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/* Enable PhysicalIRQ bit for NS world to wake the CPU */
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write_scr_el3(scr | SCR_IRQ_BIT);
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isb();
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dsb();
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wfi();
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/*
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* Restore SCR to the original value, synchronisation of scr_el3 is
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* done by eret while el3_exit to save some execution cycles.
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*/
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write_scr_el3(scr);
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}
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/*******************************************************************************
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* RockChip handler called when a power domain is about to be turned on. The
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* mpidr determines the CPU to be turned on.
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******************************************************************************/
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int rockchip_pwr_domain_on(u_register_t mpidr)
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{
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return rockchip_soc_cores_pwr_dm_on(mpidr, rockchip_sec_entrypoint);
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}
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/*******************************************************************************
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* RockChip handler called when a power domain is about to be turned off. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void rockchip_pwr_domain_off(const psci_power_state_t *target_state)
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{
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uint32_t lvl;
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plat_local_state_t lvl_state;
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int ret;
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assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE);
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plat_rockchip_gic_cpuif_disable();
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if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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plat_cci_disable();
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rockchip_soc_cores_pwr_dm_off();
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for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
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lvl_state = target_state->pwr_domain_state[lvl];
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ret = rockchip_soc_hlvl_pwr_dm_off(lvl, lvl_state);
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if (ret == PSCI_E_NOT_SUPPORTED)
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break;
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}
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}
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/*******************************************************************************
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* RockChip handler called when a power domain is about to be suspended. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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void rockchip_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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uint32_t lvl;
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plat_local_state_t lvl_state;
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int ret;
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if (RK_CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
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return;
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/* Prevent interrupts from spuriously waking up this cpu */
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plat_rockchip_gic_cpuif_disable();
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if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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rockchip_soc_sys_pwr_dm_suspend();
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else
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rockchip_soc_cores_pwr_dm_suspend();
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/* Perform the common cluster specific operations */
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if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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plat_cci_disable();
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if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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return;
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for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
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lvl_state = target_state->pwr_domain_state[lvl];
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ret = rockchip_soc_hlvl_pwr_dm_suspend(lvl, lvl_state);
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if (ret == PSCI_E_NOT_SUPPORTED)
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break;
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}
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}
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/*******************************************************************************
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* RockChip handler called when a power domain has just been powered on after
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* being turned off earlier. The target_state encodes the low power state that
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* each level has woken up from.
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******************************************************************************/
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void rockchip_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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uint32_t lvl;
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plat_local_state_t lvl_state;
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int ret;
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assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE);
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for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
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lvl_state = target_state->pwr_domain_state[lvl];
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ret = rockchip_soc_hlvl_pwr_dm_on_finish(lvl, lvl_state);
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if (ret == PSCI_E_NOT_SUPPORTED)
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break;
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}
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rockchip_soc_cores_pwr_dm_on_finish();
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/* Perform the common cluster specific operations */
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if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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/* Enable coherency if this cluster was off */
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plat_cci_enable();
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}
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/* Enable the gic cpu interface */
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plat_rockchip_gic_pcpu_init();
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/* Program the gic per-cpu distributor or re-distributor interface */
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plat_rockchip_gic_cpuif_enable();
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}
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/*******************************************************************************
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* RockChip handler called when a power domain has just been powered on after
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* having been suspended earlier. The target_state encodes the low power state
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* that each level has woken up from.
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* TODO: At the moment we reuse the on finisher and reinitialize the secure
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* context. Need to implement a separate suspend finisher.
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******************************************************************************/
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void rockchip_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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uint32_t lvl;
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plat_local_state_t lvl_state;
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int ret;
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/* Nothing to be done on waking up from retention from CPU level */
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if (RK_CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
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return;
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if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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rockchip_soc_sys_pwr_dm_resume();
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goto comm_finish;
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}
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for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
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lvl_state = target_state->pwr_domain_state[lvl];
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ret = rockchip_soc_hlvl_pwr_dm_resume(lvl, lvl_state);
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if (ret == PSCI_E_NOT_SUPPORTED)
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break;
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}
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rockchip_soc_cores_pwr_dm_resume();
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/*
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* Program the gic per-cpu distributor or re-distributor interface.
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* For sys power domain operation, resuming of the gic needs to operate
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* in rockchip_soc_sys_pwr_dm_resume(), according to the sys power mode
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* implements.
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*/
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plat_rockchip_gic_cpuif_enable();
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comm_finish:
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/* Perform the common cluster specific operations */
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if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
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/* Enable coherency if this cluster was off */
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plat_cci_enable();
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}
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}
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/*******************************************************************************
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* RockChip handlers to reboot the system
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******************************************************************************/
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static void __dead2 rockchip_system_reset(void)
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{
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rockchip_soc_soft_reset();
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}
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/*******************************************************************************
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* RockChip handlers to power off the system
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******************************************************************************/
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static void __dead2 rockchip_system_poweroff(void)
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{
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rockchip_soc_system_off();
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}
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static void __dead2 rockchip_pd_pwr_down_wfi(
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const psci_power_state_t *target_state)
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{
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if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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rockchip_soc_sys_pd_pwr_dn_wfi();
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else
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rockchip_soc_cores_pd_pwr_dn_wfi(target_state);
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}
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/*******************************************************************************
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* Export the platform handlers via plat_rockchip_psci_pm_ops. The rockchip
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* standard
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* platform layer will take care of registering the handlers with PSCI.
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******************************************************************************/
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const plat_psci_ops_t plat_rockchip_psci_pm_ops = {
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.cpu_standby = rockchip_cpu_standby,
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.pwr_domain_on = rockchip_pwr_domain_on,
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.pwr_domain_off = rockchip_pwr_domain_off,
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.pwr_domain_suspend = rockchip_pwr_domain_suspend,
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.pwr_domain_on_finish = rockchip_pwr_domain_on_finish,
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.pwr_domain_suspend_finish = rockchip_pwr_domain_suspend_finish,
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.pwr_domain_pwr_down_wfi = rockchip_pd_pwr_down_wfi,
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.system_reset = rockchip_system_reset,
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.system_off = rockchip_system_poweroff,
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.validate_power_state = rockchip_validate_power_state,
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.get_sys_suspend_power_state = rockchip_get_sys_suspend_power_state
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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*psci_ops = &plat_rockchip_psci_pm_ops;
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rockchip_sec_entrypoint = sec_entrypoint;
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return 0;
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}
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uintptr_t plat_get_sec_entrypoint(void)
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{
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assert(rockchip_sec_entrypoint);
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return rockchip_sec_entrypoint;
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}
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