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332 lines
8.6 KiB
332 lines
8.6 KiB
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PMU_H__
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#define __PMU_H__
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/* Needed aligned 16 bytes for sp stack top */
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#define PSRAM_SP_TOP ((PMUSRAM_BASE + PMUSRAM_RSIZE) & ~0xf)
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/*****************************************************************************
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* pmu con,reg
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*****************************************************************************/
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#define PMU_WKUP_CFG0_LO 0x00
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#define PMU_WKUP_CFG0_HI 0x04
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#define PMU_WKUP_CFG1_LO 0x08
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#define PMU_WKUP_CFG1_HI 0x0c
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#define PMU_WKUP_CFG2_LO 0x10
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#define PMU_PWRDN_CON 0x18
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#define PMU_PWRDN_ST 0x20
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#define PMU_PWRMODE_CORE_LO 0x24
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#define PMU_PWRMODE_CORE_HI 0x28
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#define PMU_PWRMODE_COMMON_CON_LO 0x2c
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#define PMU_PWRMODE_COMMON_CON_HI 0x30
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#define PMU_SFT_CON 0x34
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#define PMU_INT_ST 0x44
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#define PMU_BUS_IDLE_REQ 0x64
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#define PMU_BUS_IDLE_ST 0x6c
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#define PMU_OSC_CNT_LO 0x74
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#define PMU_OSC_CNT_HI 0x78
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#define PMU_PLLLOCK_CNT_LO 0x7c
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#define PMU_PLLLOCK_CNT_HI 0x80
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#define PMU_PLLRST_CNT_LO 0x84
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#define PMU_PLLRST_CNT_HI 0x88
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#define PMU_STABLE_CNT_LO 0x8c
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#define PMU_STABLE_CNT_HI 0x90
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#define PMU_WAKEUP_RST_CLR_LO 0x9c
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#define PMU_WAKEUP_RST_CLR_HI 0xa0
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#define PMU_DDR_SREF_ST 0xa4
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#define PMU_SYS_REG0_LO 0xa8
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#define PMU_SYS_REG0_HI 0xac
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#define PMU_SYS_REG1_LO 0xb0
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#define PMU_SYS_REG1_HI 0xb4
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#define PMU_SYS_REG2_LO 0xb8
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#define PMU_SYS_REG2_HI 0xbc
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#define PMU_SYS_REG3_LO 0xc0
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#define PMU_SYS_REG3_HI 0xc4
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#define PMU_SCU_PWRDN_CNT_LO 0xc8
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#define PMU_SCU_PWRDN_CNT_HI 0xcc
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#define PMU_SCU_PWRUP_CNT_LO 0xd0
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#define PMU_SCU_PWRUP_CNT_HI 0xd4
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#define PMU_TIMEOUT_CNT_LO 0xd8
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#define PMU_TIMEOUT_CNT_HI 0xdc
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#define PMU_CPUAPM_CON(cpu) (0xe0 + (cpu) * 0x4)
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#define CORES_PM_DISABLE 0x0
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#define CLST_CPUS_MSK 0xf
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#define PD_CTR_LOOP 500
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#define PD_CHECK_LOOP 500
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#define WFEI_CHECK_LOOP 500
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#define BUS_IDLE_LOOP 1000
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enum pmu_wkup_cfg2 {
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pmu_cluster_wkup_en = 0,
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pmu_gpio_wkup_en = 2,
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pmu_sdio_wkup_en = 3,
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pmu_sdmmc_wkup_en = 4,
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pmu_uart0_wkup_en = 5,
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pmu_timer_wkup_en = 6,
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pmu_usbdev_wkup_en = 7,
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pmu_sft_wkup_en = 8,
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pmu_timeout_wkup_en = 10,
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};
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enum pmu_powermode_core_lo {
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pmu_global_int_dis = 0,
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pmu_core_src_gt = 1,
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pmu_cpu0_pd = 3,
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pmu_clr_core = 5,
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pmu_scu_pd = 6,
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pmu_l2_idle = 8,
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pmu_l2_flush = 9,
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pmu_clr_bus2main = 10,
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pmu_clr_peri2msch = 11,
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};
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enum pmu_powermode_core_hi {
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pmu_apll_pd_en = 3,
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pmu_dpll_pd_en = 4,
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pmu_cpll_pd_en = 5,
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pmu_gpll_pd_en = 6,
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pmu_npll_pd_en = 7,
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};
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enum pmu_powermode_common_lo {
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pmu_mode_en = 0,
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pmu_ddr_pd_en = 1,
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pmu_wkup_rst = 3,
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pmu_pll_pd = 4,
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pmu_pmu_use_if = 6,
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pmu_alive_use_if = 7,
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pmu_osc_dis = 8,
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pmu_input_clamp = 9,
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pmu_sref_enter = 10,
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pmu_ddrc_gt = 11,
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pmu_ddrio_ret = 12,
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pmu_ddrio_ret_deq = 13,
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pmu_clr_pmu = 14,
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pmu_clr_peri_pmu = 15,
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};
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enum pmu_powermode_common_hi {
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pmu_clr_bus = 0,
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pmu_clr_mmc = 1,
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pmu_clr_msch = 2,
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pmu_clr_nandc = 3,
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pmu_clr_gmac = 4,
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pmu_clr_vo = 5,
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pmu_clr_vi = 6,
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pmu_clr_gpu = 7,
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pmu_clr_usb = 8,
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pmu_clr_vpu = 9,
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pmu_clr_crypto = 10,
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pmu_wakeup_begin_cfg = 11,
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pmu_peri_clk_src_gt = 12,
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pmu_bus_clk_src_gt = 13,
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};
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enum pmu_pd_id {
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PD_CPU0 = 0,
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PD_CPU1 = 1,
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PD_CPU2 = 2,
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PD_CPU3 = 3,
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PD_SCU = 4,
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PD_USB = 5,
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PD_DDR = 6,
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PD_SDCARD = 8,
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PD_CRYPTO = 9,
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PD_GMAC = 10,
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PD_MMC_NAND = 11,
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PD_VPU = 12,
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PD_VO = 13,
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PD_VI = 14,
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PD_GPU = 15,
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PD_END = 16,
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};
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enum pmu_bus_id {
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BUS_ID_BUS = 0,
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BUS_ID_BUS2MAIN = 1,
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BUS_ID_GPU = 2,
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BUS_ID_CORE = 3,
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BUS_ID_CRYPTO = 4,
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BUS_ID_MMC = 5,
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BUS_ID_GMAC = 6,
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BUS_ID_VO = 7,
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BUS_ID_VI = 8,
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BUS_ID_SDCARD = 9,
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BUS_ID_USB = 10,
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BUS_ID_MSCH = 11,
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BUS_ID_PERI = 12,
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BUS_ID_PMU = 13,
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BUS_ID_VPU = 14,
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BUS_ID_PERI2MSCH = 15,
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};
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enum pmu_pd_state {
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pmu_pd_on = 0,
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pmu_pd_off = 1
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};
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enum pmu_bus_state {
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bus_active = 0,
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bus_idle = 1,
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};
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enum cores_pm_ctr_mode {
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core_pwr_pd = 0,
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core_pwr_wfi = 1,
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core_pwr_wfi_int = 2
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};
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enum pmu_cores_pm_by_wfi {
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core_pm_en = 0,
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core_pm_int_wakeup_en,
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core_pm_dis_int,
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core_pm_sft_wakeup_en
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};
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/*****************************************************************************
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* pmu_sgrf
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*****************************************************************************/
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#define PMUSGRF_SOC_CON(i) ((i) * 0x4)
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/*****************************************************************************
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* pmu_grf
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*****************************************************************************/
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#define GPIO0A_IOMUX 0x0
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#define GPIO0B_IOMUX 0x4
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#define GPIO0C_IOMUX 0x8
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#define GPIO0A_PULL 0x10
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#define GPIO0L_SMT 0x38
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#define GPIO0H_SMT 0x3c
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#define PMUGRF_SOC_CON(i) (0x100 + (i) * 4)
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#define PMUGRF_PVTM_CON0 0x180
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#define PMUGRF_PVTM_CON1 0x184
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#define PMUGRF_PVTM_ST0 0x190
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#define PMUGRF_PVTM_ST1 0x194
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#define PVTM_CALC_CNT 0x200
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#define PMUGRF_OS_REG(n) (0x200 + (n) * 4)
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#define GPIO0A6_IOMUX_MSK (0x3 << 12)
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#define GPIO0A6_IOMUX_GPIO (0x0 << 12)
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#define GPIO0A6_IOMUX_RSTOUT (0x1 << 12)
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#define GPIO0A6_IOMUX_SHTDN (0x2 << 12)
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enum px30_pmugrf_pvtm_con0 {
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pgrf_pvtm_st = 0,
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pgrf_pvtm_en = 1,
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pgrf_pvtm_div = 2,
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};
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/*****************************************************************************
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* pmu_cru
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*****************************************************************************/
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#define CRU_PMU_MODE 0x20
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#define CRU_PMU_CLKSEL_CON 0x40
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#define CRU_PMU_CLKSELS_CON(i) (CRU_PMU_CLKSEL_CON + (i) * 4)
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#define CRU_PMU_CLKSEL_CON_CNT 5
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#define CRU_PMU_CLKGATE_CON 0x80
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#define CRU_PMU_CLKGATES_CON(i) (CRU_PMU_CLKGATE_CON + (i) * 4)
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#define CRU_PMU_CLKGATE_CON_CNT 2
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#define CRU_PMU_ATCS_CON 0xc0
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#define CRU_PMU_ATCSS_CON(i) (CRU_PMU_ATCS_CON + (i) * 4)
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#define CRU_PMU_ATCS_CON_CNT 2
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/*****************************************************************************
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* pmusgrf
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*****************************************************************************/
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#define PMUSGRF_RSTOUT_EN (0x7 << 10)
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#define PMUSGRF_RSTOUT_FST 10
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#define PMUSGRF_RSTOUT_TSADC 11
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#define PMUSGRF_RSTOUT_WDT 12
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#define PMUGRF_SOC_CON2_US_WMSK (0x1fff << 16)
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#define PMUGRF_SOC_CON2_MAX_341US 0x1fff
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#define PMUGRF_SOC_CON2_200US 0x12c0
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#define PMUGRF_FAILSAFE_SHTDN_TSADC BIT(0)
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#define PMUGRF_FAILSAFE_SHTDN_WDT BIT(1)
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/*****************************************************************************
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* QOS
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*****************************************************************************/
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#define CPU_AXI_QOS_ID_COREID 0x00
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#define CPU_AXI_QOS_REVISIONID 0x04
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#define CPU_AXI_QOS_PRIORITY 0x08
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#define CPU_AXI_QOS_MODE 0x0c
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#define CPU_AXI_QOS_BANDWIDTH 0x10
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#define CPU_AXI_QOS_SATURATION 0x14
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#define CPU_AXI_QOS_EXTCONTROL 0x18
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#define CPU_AXI_QOS_NUM_REGS 0x07
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#define CPU_AXI_CPU_QOS_BASE 0xff508000
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#define CPU_AXI_GPU_QOS_BASE 0xff520000
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#define CPU_AXI_ISP_128M_QOS_BASE 0xff548000
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#define CPU_AXI_ISP_RD_QOS_BASE 0xff548080
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#define CPU_AXI_ISP_WR_QOS_BASE 0xff548100
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#define CPU_AXI_ISP_M1_QOS_BASE 0xff548180
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#define CPU_AXI_VIP_QOS_BASE 0xff548200
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#define CPU_AXI_RGA_RD_QOS_BASE 0xff550000
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#define CPU_AXI_RGA_WR_QOS_BASE 0xff550080
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#define CPU_AXI_VOP_M0_QOS_BASE 0xff550100
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#define CPU_AXI_VOP_M1_QOS_BASE 0xff550180
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#define CPU_AXI_VPU_QOS_BASE 0xff558000
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#define CPU_AXI_VPU_R128_QOS_BASE 0xff558080
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#define CPU_AXI_DCF_QOS_BASE 0xff500000
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#define CPU_AXI_DMAC_QOS_BASE 0xff500080
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#define CPU_AXI_CRYPTO_QOS_BASE 0xff510000
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#define CPU_AXI_GMAC_QOS_BASE 0xff518000
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#define CPU_AXI_EMMC_QOS_BASE 0xff538000
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#define CPU_AXI_NAND_QOS_BASE 0xff538080
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#define CPU_AXI_SDIO_QOS_BASE 0xff538100
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#define CPU_AXI_SFC_QOS_BASE 0xff538180
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#define CPU_AXI_SDMMC_QOS_BASE 0xff52c000
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#define CPU_AXI_USB_HOST_QOS_BASE 0xff540000
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#define CPU_AXI_USB_OTG_QOS_BASE 0xff540080
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#define PX30_CPU_AXI_SAVE_QOS(array, base) do { \
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array[0] = mmio_read_32(base + CPU_AXI_QOS_ID_COREID); \
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array[1] = mmio_read_32(base + CPU_AXI_QOS_REVISIONID); \
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array[2] = mmio_read_32(base + CPU_AXI_QOS_PRIORITY); \
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array[3] = mmio_read_32(base + CPU_AXI_QOS_MODE); \
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array[4] = mmio_read_32(base + CPU_AXI_QOS_BANDWIDTH); \
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array[5] = mmio_read_32(base + CPU_AXI_QOS_SATURATION); \
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array[6] = mmio_read_32(base + CPU_AXI_QOS_EXTCONTROL); \
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} while (0)
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#define PX30_CPU_AXI_RESTORE_QOS(array, base) do { \
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mmio_write_32(base + CPU_AXI_QOS_ID_COREID, array[0]); \
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mmio_write_32(base + CPU_AXI_QOS_REVISIONID, array[1]); \
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mmio_write_32(base + CPU_AXI_QOS_PRIORITY, array[2]); \
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mmio_write_32(base + CPU_AXI_QOS_MODE, array[3]); \
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mmio_write_32(base + CPU_AXI_QOS_BANDWIDTH, array[4]); \
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mmio_write_32(base + CPU_AXI_QOS_SATURATION, array[5]); \
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mmio_write_32(base + CPU_AXI_QOS_EXTCONTROL, array[6]); \
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} while (0)
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#define SAVE_QOS(array, NAME) \
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PX30_CPU_AXI_SAVE_QOS(array, CPU_AXI_##NAME##_QOS_BASE)
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#define RESTORE_QOS(array, NAME) \
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PX30_CPU_AXI_RESTORE_QOS(array, CPU_AXI_##NAME##_QOS_BASE)
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#endif /* __PMU_H__ */
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