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157 lines
3.1 KiB
157 lines
3.1 KiB
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DRAM_H
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#define DRAM_H
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#include <stdint.h>
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#include <dram_regs.h>
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#include <plat_private.h>
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enum {
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DDR3 = 3,
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LPDDR2 = 5,
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LPDDR3 = 6,
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LPDDR4 = 7,
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UNUSED = 0xff
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};
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struct rk3399_ddr_pctl_regs {
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uint32_t denali_ctl[CTL_REG_NUM];
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};
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struct rk3399_ddr_publ_regs {
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/*
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* PHY registers from 0 to 90 for slice1.
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* These are used to restore slice1-4 on resume.
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*/
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uint32_t phy0[91];
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/*
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* PHY registers from 512 to 895.
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* Only registers 0-37 of each 128 register range are used.
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*/
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uint32_t phy512[3][38];
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uint32_t phy896[63];
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};
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struct rk3399_ddr_pi_regs {
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uint32_t denali_pi[PI_REG_NUM];
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};
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union noc_ddrtiminga0 {
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uint32_t d32;
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struct {
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unsigned acttoact : 6;
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unsigned reserved0 : 2;
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unsigned rdtomiss : 6;
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unsigned reserved1 : 2;
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unsigned wrtomiss : 6;
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unsigned reserved2 : 2;
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unsigned readlatency : 8;
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} b;
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};
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union noc_ddrtimingb0 {
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uint32_t d32;
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struct {
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unsigned rdtowr : 5;
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unsigned reserved0 : 3;
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unsigned wrtord : 5;
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unsigned reserved1 : 3;
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unsigned rrd : 4;
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unsigned reserved2 : 4;
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unsigned faw : 6;
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unsigned reserved3 : 2;
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} b;
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};
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union noc_ddrtimingc0 {
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uint32_t d32;
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struct {
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unsigned burstpenalty : 4;
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unsigned reserved0 : 4;
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unsigned wrtomwr : 6;
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unsigned reserved1 : 18;
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} b;
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};
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union noc_devtodev0 {
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uint32_t d32;
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struct {
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unsigned busrdtord : 3;
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unsigned reserved0 : 1;
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unsigned busrdtowr : 3;
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unsigned reserved1 : 1;
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unsigned buswrtord : 3;
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unsigned reserved2 : 1;
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unsigned buswrtowr : 3;
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unsigned reserved3 : 17;
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} b;
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};
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union noc_ddrmode {
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uint32_t d32;
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struct {
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unsigned autoprecharge : 1;
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unsigned bypassfiltering : 1;
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unsigned fawbank : 1;
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unsigned burstsize : 2;
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unsigned mwrsize : 2;
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unsigned reserved2 : 1;
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unsigned forceorder : 8;
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unsigned forceorderstate : 8;
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unsigned reserved3 : 8;
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} b;
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};
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struct rk3399_msch_timings {
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union noc_ddrtiminga0 ddrtiminga0;
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union noc_ddrtimingb0 ddrtimingb0;
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union noc_ddrtimingc0 ddrtimingc0;
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union noc_devtodev0 devtodev0;
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union noc_ddrmode ddrmode;
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uint32_t agingx0;
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};
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struct rk3399_sdram_channel {
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unsigned char rank;
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/* col = 0, means this channel is invalid */
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unsigned char col;
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/* 3:8bank, 2:4bank */
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unsigned char bk;
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/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
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unsigned char bw;
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/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
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unsigned char dbw;
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/* row_3_4 = 1: 6Gb or 12Gb die
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* row_3_4 = 0: normal die, power of 2
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*/
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unsigned char row_3_4;
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unsigned char cs0_row;
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unsigned char cs1_row;
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uint32_t ddrconfig;
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struct rk3399_msch_timings noc_timings;
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};
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struct rk3399_sdram_params {
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struct rk3399_sdram_channel ch[2];
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uint32_t ddr_freq;
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unsigned char dramtype;
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unsigned char num_channels;
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unsigned char stride;
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unsigned char odt;
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struct rk3399_ddr_pctl_regs pctl_regs;
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struct rk3399_ddr_pi_regs pi_regs;
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struct rk3399_ddr_publ_regs phy_regs;
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uint32_t rx_cal_dqs[2][4];
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};
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extern __sramdata struct rk3399_sdram_params sdram_config;
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void dram_init(void);
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#endif /* DRAM_H */
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