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168 lines
5.2 KiB
168 lines
5.2 KiB
/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <plat_private.h>
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#include <secure.h>
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#include <soc.h>
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static void sgrf_ddr_rgn_global_bypass(uint32_t bypass)
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{
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if (bypass)
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/* set bypass (non-secure regions) for whole ddr regions */
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mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
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SGRF_DDR_RGN_BYPS);
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else
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/* cancel bypass for whole ddr regions */
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mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
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SGRF_DDR_RGN_NO_BYPS);
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}
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/**
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* There are 8 + 1 regions for DDR secure control:
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* DDR_RGN_0 ~ DDR_RGN_7: Per DDR_RGNs grain size is 1MB
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* DDR_RGN_X - the memories of exclude DDR_RGN_0 ~ DDR_RGN_7
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*
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* DDR_RGN_0 - start address of the RGN0
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* DDR_RGN_8 - end address of the RGN0
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* DDR_RGN_1 - start address of the RGN1
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* DDR_RGN_9 - end address of the RGN1
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* ...
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* DDR_RGN_7 - start address of the RGN7
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* DDR_RGN_15 - end address of the RGN7
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* DDR_RGN_16 - bit 0 ~ 7 is bitmap for RGN0~7 secure,0: disable, 1: enable
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* bit 8 is setting for RGNx, the rest of the memory and region
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* which excludes RGN0~7, 0: disable, 1: enable
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* bit 9, the global secure configuration via bypass, 0: disable
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* bypass, 1: enable bypass
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*
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* @rgn - the DDR regions 0 ~ 7 which are can be configured.
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* @st - start address to set as secure
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* @sz - length of area to set as secure
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* The @st_mb and @ed_mb indicate the start and end addresses for which to set
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* the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the
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* address range 0x0 ~ 0xfffff is secure.
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*
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* For example, if we would like to set the range [0, 32MB) is security via
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* DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31.
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*/
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static void sgrf_ddr_rgn_config(uint32_t rgn,
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uintptr_t st, size_t sz)
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{
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uintptr_t ed = st + sz;
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uintptr_t st_mb, ed_mb;
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assert(rgn <= 7);
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assert(st < ed);
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/* check aligned 1MB */
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assert(st % SIZE_M(1) == 0);
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assert(ed % SIZE_M(1) == 0);
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st_mb = st / SIZE_M(1);
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ed_mb = ed / SIZE_M(1);
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/* set ddr region addr start */
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mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn),
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BITS_WITH_WMASK(st_mb, SGRF_DDR_RGN_0_16_WMSK, 0));
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/* set ddr region addr end */
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mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn + 8),
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BITS_WITH_WMASK((ed_mb - 1), SGRF_DDR_RGN_0_16_WMSK, 0));
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mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
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BIT_WITH_WMSK(rgn));
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}
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void secure_watchdog_gate(void)
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{
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/**
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* Disable CA53 and CM0 wdt pclk
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* BIT[8]: ca53 wdt pclk, 0: enable 1: disable
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* BIT[10]: cm0 wdt pclk, 0: enable 1: disable
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*/
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3),
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BIT_WITH_WMSK(PCLK_WDT_CA53_GATE_SHIFT) |
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BIT_WITH_WMSK(PCLK_WDT_CM0_GATE_SHIFT));
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}
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__pmusramfunc void secure_watchdog_ungate(void)
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{
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/**
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* Enable CA53 and CM0 wdt pclk
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* BIT[8]: ca53 wdt pclk, 0: enable 1: disable
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* BIT[10]: cm0 wdt pclk, 0: enable 1: disable
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*/
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3),
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WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) |
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WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT));
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}
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__pmusramfunc void sram_secure_timer_init(void)
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{
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mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff);
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mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff);
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mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
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mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
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/* auto reload & enable the timer */
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mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
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TIMER_EN | TIMER_FMODE);
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}
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void secure_timer_init(void)
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{
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mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff);
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mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff);
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mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
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mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
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/* auto reload & enable the timer */
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mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
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TIMER_EN | TIMER_FMODE);
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}
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void secure_sgrf_init(void)
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{
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/* security config for master */
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5),
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REG_SOC_WMSK | SGRF_SOC_ALLMST_NS);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6),
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REG_SOC_WMSK | SGRF_SOC_ALLMST_NS);
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mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7),
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REG_SOC_WMSK | SGRF_SOC_ALLMST_NS);
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/* security config for slave */
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mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0),
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SGRF_PMU_SLV_S_CFGED |
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SGRF_PMU_SLV_CRYPTO1_NS);
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mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1),
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SGRF_SLV_S_WMSK | SGRF_PMUSRAM_S);
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mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0),
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SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
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mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1),
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SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
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mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2),
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SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
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mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3),
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SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
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mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4),
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SGRF_SLV_S_WMSK | SGRF_INTSRAM_S);
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}
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void secure_sgrf_ddr_rgn_init(void)
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{
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sgrf_ddr_rgn_config(0, TZRAM_BASE, TZRAM_SIZE);
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sgrf_ddr_rgn_global_bypass(0);
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}
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