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363 lines
9.1 KiB
363 lines
9.1 KiB
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <dfs.h>
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#include <dram.h>
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#include <m0_ctl.h>
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#include <plat_private.h>
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#include <pmu.h>
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#include <rk3399_def.h>
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#include <secure.h>
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#include <soc.h>
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/* Table of regions to map using the MMU. */
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const mmap_region_t plat_rk_mmap[] = {
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MAP_REGION_FLAT(DEV_RNG0_BASE, DEV_RNG0_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE),
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{ 0 }
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};
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/* The RockChip power domain tree descriptor */
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const unsigned char rockchip_power_domain_tree_desc[] = {
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/* No of root nodes */
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PLATFORM_SYSTEM_COUNT,
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/* No of children for the root node */
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PLATFORM_CLUSTER_COUNT,
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/* No of children for the first cluster node */
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PLATFORM_CLUSTER0_CORE_COUNT,
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/* No of children for the second cluster node */
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PLATFORM_CLUSTER1_CORE_COUNT
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};
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/* sleep data for pll suspend */
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static struct deepsleep_data_s slp_data;
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/* sleep data that needs to be accessed from pmusram */
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__pmusramdata struct pmu_sleep_data pmu_slp_data;
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static void set_pll_slow_mode(uint32_t pll_id)
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{
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if (pll_id == PPLL_ID)
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mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE);
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else
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mmio_write_32((CRU_BASE +
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CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE);
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}
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static void set_pll_normal_mode(uint32_t pll_id)
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{
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if (pll_id == PPLL_ID)
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mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE);
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else
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mmio_write_32(CRU_BASE +
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CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE);
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}
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static void set_pll_bypass(uint32_t pll_id)
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{
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if (pll_id == PPLL_ID)
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mmio_write_32(PMUCRU_BASE +
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PMUCRU_PPLL_CON(3), PLL_BYPASS_MODE);
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else
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mmio_write_32(CRU_BASE +
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CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE);
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}
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static void _pll_suspend(uint32_t pll_id)
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{
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set_pll_slow_mode(pll_id);
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set_pll_bypass(pll_id);
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}
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/**
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* disable_dvfs_plls - To suspend the specific PLLs
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*
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* When we close the center logic, the DPLL will be closed,
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* so we need to keep the ABPLL and switch to it to supply
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* clock for DDR during suspend, then we should not close
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* the ABPLL and exclude ABPLL_ID.
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*/
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void disable_dvfs_plls(void)
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{
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_pll_suspend(CPLL_ID);
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_pll_suspend(NPLL_ID);
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_pll_suspend(VPLL_ID);
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_pll_suspend(GPLL_ID);
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_pll_suspend(ALPLL_ID);
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}
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/**
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* disable_nodvfs_plls - To suspend the PPLL
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*/
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void disable_nodvfs_plls(void)
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{
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_pll_suspend(PPLL_ID);
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}
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/**
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* restore_pll - Copy PLL settings from memory to a PLL.
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*
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* This will copy PLL settings from an array in memory to the memory mapped
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* registers for a PLL.
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*
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* Note that: above the PLL exclude PPLL.
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*
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* pll_id: One of the values from enum plls_id
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* src: Pointer to the array of values to restore from
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*/
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static void restore_pll(int pll_id, uint32_t *src)
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{
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/* Nice to have PLL off while configuring */
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mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE);
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mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK);
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mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK);
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mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]);
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mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK);
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mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK);
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/* Do PLL_CON3 since that will enable things */
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mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK);
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/* Wait for PLL lock done */
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while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) &
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0x80000000) == 0x0)
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;
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}
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/**
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* save_pll - Copy PLL settings a PLL to memory
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*
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* This will copy PLL settings from the memory mapped registers for a PLL to
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* an array in memory.
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*
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* Note that: above the PLL exclude PPLL.
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*
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* pll_id: One of the values from enum plls_id
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* src: Pointer to the array of values to save to.
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*/
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static void save_pll(uint32_t *dst, int pll_id)
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{
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int i;
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for (i = 0; i < PLL_CON_COUNT; i++)
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dst[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i));
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}
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/**
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* prepare_abpll_for_ddrctrl - Copy DPLL settings to ABPLL
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*
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* This will copy DPLL settings from the memory mapped registers for a PLL to
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* an array in memory.
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*/
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void prepare_abpll_for_ddrctrl(void)
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{
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save_pll(slp_data.plls_con[ABPLL_ID], ABPLL_ID);
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save_pll(slp_data.plls_con[DPLL_ID], DPLL_ID);
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restore_pll(ABPLL_ID, slp_data.plls_con[DPLL_ID]);
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}
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void restore_abpll(void)
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{
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restore_pll(ABPLL_ID, slp_data.plls_con[ABPLL_ID]);
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}
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void clk_gate_con_save(void)
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{
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uint32_t i = 0;
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for (i = 0; i < PMUCRU_GATE_COUNT; i++)
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slp_data.pmucru_gate_con[i] =
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mmio_read_32(PMUCRU_BASE + PMUCRU_GATE_CON(i));
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for (i = 0; i < CRU_GATE_COUNT; i++)
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slp_data.cru_gate_con[i] =
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mmio_read_32(CRU_BASE + CRU_GATE_CON(i));
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}
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void clk_gate_con_disable(void)
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{
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uint32_t i;
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for (i = 0; i < PMUCRU_GATE_COUNT; i++)
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mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), REG_SOC_WMSK);
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for (i = 0; i < CRU_GATE_COUNT; i++)
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mmio_write_32(CRU_BASE + CRU_GATE_CON(i), REG_SOC_WMSK);
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}
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void clk_gate_con_restore(void)
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{
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uint32_t i;
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for (i = 0; i < PMUCRU_GATE_COUNT; i++)
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mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i),
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REG_SOC_WMSK | slp_data.pmucru_gate_con[i]);
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for (i = 0; i < CRU_GATE_COUNT; i++)
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mmio_write_32(CRU_BASE + CRU_GATE_CON(i),
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REG_SOC_WMSK | slp_data.cru_gate_con[i]);
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}
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static void set_plls_nobypass(uint32_t pll_id)
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{
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if (pll_id == PPLL_ID)
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mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3),
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PLL_NO_BYPASS_MODE);
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else
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mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3),
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PLL_NO_BYPASS_MODE);
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}
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static void _pll_resume(uint32_t pll_id)
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{
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set_plls_nobypass(pll_id);
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set_pll_normal_mode(pll_id);
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}
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void set_pmu_rsthold(void)
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{
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uint32_t rstnhold_cofig0;
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uint32_t rstnhold_cofig1;
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pmu_slp_data.pmucru_rstnhold_con0 = mmio_read_32(PMUCRU_BASE +
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PMUCRU_RSTNHOLD_CON0);
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pmu_slp_data.pmucru_rstnhold_con1 = mmio_read_32(PMUCRU_BASE +
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PMUCRU_RSTNHOLD_CON1);
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rstnhold_cofig0 = BIT_WITH_WMSK(PRESETN_NOC_PMU_HOLD) |
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BIT_WITH_WMSK(PRESETN_INTMEM_PMU_HOLD) |
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BIT_WITH_WMSK(HRESETN_CM0S_PMU_HOLD) |
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BIT_WITH_WMSK(HRESETN_CM0S_NOC_PMU_HOLD) |
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BIT_WITH_WMSK(DRESETN_CM0S_PMU_HOLD) |
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BIT_WITH_WMSK(POESETN_CM0S_PMU_HOLD) |
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BIT_WITH_WMSK(PRESETN_TIMER_PMU_0_1_HOLD) |
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BIT_WITH_WMSK(RESETN_TIMER_PMU_0_HOLD) |
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BIT_WITH_WMSK(RESETN_TIMER_PMU_1_HOLD) |
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BIT_WITH_WMSK(PRESETN_UART_M0_PMU_HOLD) |
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BIT_WITH_WMSK(RESETN_UART_M0_PMU_HOLD) |
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BIT_WITH_WMSK(PRESETN_WDT_PMU_HOLD);
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rstnhold_cofig1 = BIT_WITH_WMSK(PRESETN_RKPWM_PMU_HOLD) |
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BIT_WITH_WMSK(PRESETN_PMUGRF_HOLD) |
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BIT_WITH_WMSK(PRESETN_SGRF_HOLD) |
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BIT_WITH_WMSK(PRESETN_GPIO0_HOLD) |
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BIT_WITH_WMSK(PRESETN_GPIO1_HOLD) |
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BIT_WITH_WMSK(PRESETN_CRU_PMU_HOLD) |
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BIT_WITH_WMSK(PRESETN_PVTM_PMU_HOLD);
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mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0, rstnhold_cofig0);
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mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON1, rstnhold_cofig1);
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}
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void pmu_sgrf_rst_hld(void)
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{
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mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),
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CRU_PMU_SGRF_RST_HOLD);
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}
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/*
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* When system reset in running state, we want the cpus to be reboot
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* from maskrom (system reboot),
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* the pmusgrf reset-hold bits needs to be released.
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* When system wake up from system deep suspend, some soc will be reset
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* when waked up,
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* we want the bootcpu to be reboot from pmusram,
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* the pmusgrf reset-hold bits needs to be held.
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*/
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__pmusramfunc void pmu_sgrf_rst_hld_release(void)
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{
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mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),
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CRU_PMU_SGRF_RST_RLS);
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}
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__pmusramfunc void restore_pmu_rsthold(void)
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{
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mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0,
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pmu_slp_data.pmucru_rstnhold_con0 | REG_SOC_WMSK);
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mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON1,
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pmu_slp_data.pmucru_rstnhold_con1 | REG_SOC_WMSK);
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}
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/**
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* enable_dvfs_plls - To resume the specific PLLs
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*
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* Please see the comment at the disable_dvfs_plls()
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* we don't suspend the ABPLL, so don't need resume
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* it too.
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*/
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void enable_dvfs_plls(void)
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{
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_pll_resume(ALPLL_ID);
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_pll_resume(GPLL_ID);
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_pll_resume(VPLL_ID);
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_pll_resume(NPLL_ID);
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_pll_resume(CPLL_ID);
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}
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/**
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* enable_nodvfs_plls - To resume the PPLL
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*/
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void enable_nodvfs_plls(void)
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{
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_pll_resume(PPLL_ID);
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}
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void soc_global_soft_reset_init(void)
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{
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mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),
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CRU_PMU_SGRF_RST_RLS);
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mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON,
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CRU_PMU_WDTRST_MSK | CRU_PMU_FIRST_SFTRST_MSK);
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}
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void __dead2 soc_global_soft_reset(void)
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{
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pmu_power_domains_on();
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set_pll_slow_mode(VPLL_ID);
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set_pll_slow_mode(NPLL_ID);
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set_pll_slow_mode(GPLL_ID);
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set_pll_slow_mode(CPLL_ID);
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set_pll_slow_mode(PPLL_ID);
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set_pll_slow_mode(ABPLL_ID);
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set_pll_slow_mode(ALPLL_ID);
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dsb();
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mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL);
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/*
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* Maybe the HW needs some times to reset the system,
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* so we do not hope the core to excute valid codes.
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*/
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while (1)
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;
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}
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void plat_rockchip_soc_init(void)
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{
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secure_timer_init();
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secure_sgrf_init();
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secure_sgrf_ddr_rgn_init();
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soc_global_soft_reset_init();
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plat_rockchip_gpio_init();
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m0_init();
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dram_init();
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dram_dfs_init();
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}
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