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285 lines
7.1 KiB
285 lines
7.1 KiB
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOC_H
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#define SOC_H
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#include <lib/utils.h>
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#define GLB_SRST_FST_CFG_VAL 0xfdb9
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#define GLB_SRST_SND_CFG_VAL 0xeca8
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#define PMUCRU_PPLL_CON(n) ((n) * 4)
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#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4)
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#define PLL_MODE_MSK 0x03
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#define PLL_MODE_SHIFT 0x08
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#define PLL_BYPASS_MSK 0x01
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#define PLL_BYPASS_SHIFT 0x01
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#define PLL_PWRDN_MSK 0x01
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#define PLL_PWRDN_SHIFT 0x0
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#define PLL_BYPASS BIT(1)
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#define PLL_PWRDN BIT(0)
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#define NO_PLL_BYPASS (0x00)
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#define NO_PLL_PWRDN (0x00)
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#define FBDIV(n) ((0xfff << 16) | n)
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#define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12))
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#define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8))
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#define REFDIV(n) ((0x3F << 16) | n)
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#define PLL_LOCK(n) ((n >> 31) & 0x1)
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#define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\
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PLL_MODE_MSK, PLL_MODE_SHIFT)
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#define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\
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PLL_MODE_MSK, PLL_MODE_SHIFT)
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#define PLL_BYPASS_MODE BIT_WITH_WMSK(PLL_BYPASS_SHIFT)
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#define PLL_NO_BYPASS_MODE WMSK_BIT(PLL_BYPASS_SHIFT)
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#define PLL_CON_COUNT 0x06
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#define CRU_CLKSEL_COUNT 108
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#define CRU_CLKSEL_CON(n) (0x100 + (n) * 4)
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#define PMUCRU_CLKSEL_CONUT 0x06
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#define PMUCRU_CLKSEL_OFFSET 0x080
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#define REG_SIZE 0x04
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#define REG_SOC_WMSK 0xffff0000
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#define CLK_GATE_MASK 0x01
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#define PMUCRU_GATE_COUNT 0x03
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#define CRU_GATE_COUNT 0x23
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#define PMUCRU_GATE_CON(n) (0x100 + (n) * 4)
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#define CRU_GATE_CON(n) (0x300 + (n) * 4)
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#define PMUCRU_RSTNHOLD_CON0 0x120
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enum {
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PRESETN_NOC_PMU_HOLD = 1,
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PRESETN_INTMEM_PMU_HOLD,
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HRESETN_CM0S_PMU_HOLD,
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HRESETN_CM0S_NOC_PMU_HOLD,
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DRESETN_CM0S_PMU_HOLD,
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POESETN_CM0S_PMU_HOLD,
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PRESETN_SPI3_HOLD,
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RESETN_SPI3_HOLD,
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PRESETN_TIMER_PMU_0_1_HOLD,
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RESETN_TIMER_PMU_0_HOLD,
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RESETN_TIMER_PMU_1_HOLD,
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PRESETN_UART_M0_PMU_HOLD,
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RESETN_UART_M0_PMU_HOLD,
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PRESETN_WDT_PMU_HOLD
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};
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#define PMUCRU_RSTNHOLD_CON1 0x124
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enum {
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PRESETN_I2C0_HOLD,
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PRESETN_I2C4_HOLD,
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PRESETN_I2C8_HOLD,
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PRESETN_MAILBOX_PMU_HOLD,
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PRESETN_RKPWM_PMU_HOLD,
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PRESETN_PMUGRF_HOLD,
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PRESETN_SGRF_HOLD,
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PRESETN_GPIO0_HOLD,
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PRESETN_GPIO1_HOLD,
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PRESETN_CRU_PMU_HOLD,
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PRESETN_INTR_ARB_HOLD,
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PRESETN_PVTM_PMU_HOLD,
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RESETN_I2C0_HOLD,
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RESETN_I2C4_HOLD,
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RESETN_I2C8_HOLD
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};
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enum plls_id {
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ALPLL_ID = 0,
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ABPLL_ID,
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DPLL_ID,
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CPLL_ID,
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GPLL_ID,
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NPLL_ID,
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VPLL_ID,
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PPLL_ID,
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END_PLL_ID,
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};
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#define CLST_L_CPUS_MSK (0xf)
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#define CLST_B_CPUS_MSK (0x3)
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enum pll_work_mode {
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SLOW_MODE = 0x00,
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NORMAL_MODE = 0x01,
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DEEP_SLOW_MODE = 0x02,
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};
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enum glb_sft_reset {
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PMU_RST_BY_FIRST_SFT,
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PMU_RST_BY_SECOND_SFT = BIT(2),
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PMU_RST_NOT_BY_SFT = BIT(3),
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};
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struct pll_div {
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uint32_t mhz;
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uint32_t refdiv;
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uint32_t fbdiv;
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uint32_t postdiv1;
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uint32_t postdiv2;
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uint32_t frac;
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uint32_t freq;
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};
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struct deepsleep_data_s {
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uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT];
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uint32_t cru_gate_con[CRU_GATE_COUNT];
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uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT];
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};
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struct pmu_sleep_data {
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uint32_t pmucru_rstnhold_con0;
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uint32_t pmucru_rstnhold_con1;
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};
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/**************************************************
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* pmugrf reg, offset
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**************************************************/
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#define PMUGRF_OSREG(n) (0x300 + (n) * 4)
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/**************************************************
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* DCF reg, offset
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**************************************************/
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#define DCF_DCF_CTRL 0x0
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#define DCF_DCF_ADDR 0x8
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#define DCF_DCF_ISR 0xc
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#define DCF_DCF_TOSET 0x14
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#define DCF_DCF_TOCMD 0x18
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#define DCF_DCF_CMD_CFG 0x1c
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/* DCF_DCF_ISR */
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#define DCF_TIMEOUT (1 << 2)
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#define DCF_ERR (1 << 1)
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#define DCF_DONE (1 << 0)
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/* DCF_DCF_CTRL */
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#define DCF_VOP_HW_EN (1 << 2)
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#define DCF_STOP (1 << 1)
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#define DCF_START (1 << 0)
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#define CYCL_24M_CNT_US(us) (24 * us)
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#define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000))
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#define CYCL_32K_CNT_MS(ms) (ms * 32)
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/**************************************************
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* cru reg, offset
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**************************************************/
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#define CRU_SOFTRST_CON(n) (0x400 + (n) * 4)
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#define CRU_DMAC0_RST BIT_WITH_WMSK(3)
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/* reset release*/
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#define CRU_DMAC0_RST_RLS WMSK_BIT(3)
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#define CRU_DMAC1_RST BIT_WITH_WMSK(4)
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/* reset release*/
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#define CRU_DMAC1_RST_RLS WMSK_BIT(4)
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#define CRU_GLB_RST_CON 0x0510
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#define CRU_GLB_SRST_FST 0x0500
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#define CRU_GLB_SRST_SND 0x0504
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#define CRU_CLKGATE_CON(n) (0x300 + n * 4)
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#define PCLK_GPIO2_GATE_SHIFT 3
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#define PCLK_GPIO3_GATE_SHIFT 4
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#define PCLK_GPIO4_GATE_SHIFT 5
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/**************************************************
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* pmu cru reg, offset
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**************************************************/
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#define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4)
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/* reset hold*/
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#define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6)
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/* reset hold release*/
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#define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6)
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#define CRU_PMU_WDTRST_MSK (0x1 << 4)
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#define CRU_PMU_WDTRST_EN 0x0
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#define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2)
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#define CRU_PMU_FIRST_SFTRST_EN 0x0
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#define CRU_PMU_CLKGATE_CON(n) (0x100 + n * 4)
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#define PCLK_GPIO0_GATE_SHIFT 3
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#define PCLK_GPIO1_GATE_SHIFT 4
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#define CPU_BOOT_ADDR_WMASK 0xffff0000
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#define CPU_BOOT_ADDR_ALIGN 16
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#define GRF_IOMUX_2BIT_MASK 0x3
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#define GRF_IOMUX_GPIO 0x0
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#define GRF_GPIO4C2_IOMUX_SHIFT 4
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#define GRF_GPIO4C2_IOMUX_PWM 0x1
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#define GRF_GPIO4C6_IOMUX_SHIFT 12
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#define GRF_GPIO4C6_IOMUX_PWM 0x1
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#define PWM_CNT(n) (0x0000 + 0x10 * (n))
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#define PWM_PERIOD_HPR(n) (0x0004 + 0x10 * (n))
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#define PWM_DUTY_LPR(n) (0x0008 + 0x10 * (n))
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#define PWM_CTRL(n) (0x000c + 0x10 * (n))
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#define PWM_DISABLE (0 << 0)
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#define PWM_ENABLE (1 << 0)
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/* grf reg offset */
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#define GRF_USBPHY0_CTRL0 0x4480
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#define GRF_USBPHY0_CTRL2 0x4488
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#define GRF_USBPHY0_CTRL3 0x448c
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#define GRF_USBPHY0_CTRL12 0x44b0
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#define GRF_USBPHY0_CTRL13 0x44b4
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#define GRF_USBPHY0_CTRL15 0x44bc
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#define GRF_USBPHY0_CTRL16 0x44c0
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#define GRF_USBPHY1_CTRL0 0x4500
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#define GRF_USBPHY1_CTRL2 0x4508
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#define GRF_USBPHY1_CTRL3 0x450c
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#define GRF_USBPHY1_CTRL12 0x4530
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#define GRF_USBPHY1_CTRL13 0x4534
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#define GRF_USBPHY1_CTRL15 0x453c
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#define GRF_USBPHY1_CTRL16 0x4540
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#define GRF_GPIO2A_IOMUX 0xe000
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#define GRF_GPIO2D_HE 0xe18c
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#define GRF_DDRC0_CON0 0xe380
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#define GRF_DDRC0_CON1 0xe384
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#define GRF_DDRC1_CON0 0xe388
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#define GRF_DDRC1_CON1 0xe38c
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#define GRF_SOC_CON_BASE 0xe200
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#define GRF_SOC_CON(n) (GRF_SOC_CON_BASE + (n) * 4)
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#define GRF_IO_VSEL 0xe640
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#define CRU_CLKSEL_CON0 0x0100
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#define CRU_CLKSEL_CON6 0x0118
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#define CRU_SDIO0_CON1 0x058c
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#define PMUCRU_CLKSEL_CON0 0x0080
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#define PMUCRU_CLKGATE_CON2 0x0108
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#define PMUCRU_SOFTRST_CON0 0x0110
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#define PMUCRU_GATEDIS_CON0 0x0130
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#define PMUCRU_SOFTRST_CON(n) (PMUCRU_SOFTRST_CON0 + (n) * 4)
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/* export related and operating SoC APIs */
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void __dead2 soc_global_soft_reset(void);
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void disable_dvfs_plls(void);
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void disable_nodvfs_plls(void);
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void enable_dvfs_plls(void);
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void enable_nodvfs_plls(void);
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void prepare_abpll_for_ddrctrl(void);
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void restore_abpll(void);
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void clk_gate_con_save(void);
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void clk_gate_con_disable(void);
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void clk_gate_con_restore(void);
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void set_pmu_rsthold(void);
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void pmu_sgrf_rst_hld(void);
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__pmusramfunc void pmu_sgrf_rst_hld_release(void);
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__pmusramfunc void restore_pmu_rsthold(void);
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#endif /* SOC_H */
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