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408 lines
10 KiB
408 lines
10 KiB
/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Ben Widawsky <ben@bwidawsk.net>
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*
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*/
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#include <unistd.h>
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#include <fcntl.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#include <errno.h>
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#include <err.h>
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#include <assert.h>
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#include <sys/ioctl.h>
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#include <sys/stat.h>
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#include <sys/mman.h>
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#include "intel_io.h"
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#include "igt_core.h"
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#include "igt_gt.h"
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#include "intel_chipset.h"
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/**
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* SECTION:intel_io
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* @short_description: Register access and sideband I/O library
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* @title: I/O
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* @include: igt.h
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* @section_id: igt-gpu-tools-IO
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*
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* This library provides register I/O helpers in both a basic version and a more
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* fancy version which also handles forcewake and can optionally check registers
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* against a white-list. All register function are compatible. Hence the same
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* code can be used to decode registers with either of them, or also from a dump
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* file using intel_mmio_use_dump_file().
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*
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* Furthermore this library also provides helper functions for accessing the
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* various sideband interfaces found on Valleyview/Baytrail based platforms.
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*/
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#define FAKEKEY 0x2468ace0
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/**
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* igt_global_mmio:
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*
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* Pointer to the register range, initialized using intel_register_access_init()
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* or intel_mmio_use_dump_file(). It is not recommended to use this directly.
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*/
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void *igt_global_mmio;
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static struct _mmio_data {
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int inited;
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bool safe;
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uint32_t i915_devid;
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struct intel_register_map map;
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int key;
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} mmio_data;
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/**
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* intel_mmio_use_dump_file:
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* @file: name of the register dump file to open
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*
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* Sets up #igt_global_mmio to point at the data contained in @file. This allows
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* the same code to get reused for dumping and decoding from running hardware as
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* from register dumps.
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*/
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void
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intel_mmio_use_dump_file(char *file)
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{
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int fd;
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struct stat st;
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fd = open(file, O_RDWR);
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igt_fail_on_f(fd == -1,
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"Couldn't open %s\n", file);
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fstat(fd, &st);
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igt_global_mmio = mmap(NULL, st.st_size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
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igt_fail_on_f(igt_global_mmio == MAP_FAILED,
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"Couldn't mmap %s\n", file);
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close(fd);
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}
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/**
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* intel_mmio_use_pci_bar:
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* @pci_dev: intel gracphis pci device
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*
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* Sets up #igt_global_mmio to point at the mmio bar.
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*
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* @pci_dev can be obtained from intel_get_pci_device().
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*/
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void
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intel_mmio_use_pci_bar(struct pci_device *pci_dev)
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{
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uint32_t devid, gen;
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int mmio_bar, mmio_size;
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int error;
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devid = pci_dev->device_id;
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if (IS_GEN2(devid))
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mmio_bar = 1;
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else
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mmio_bar = 0;
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gen = intel_gen(devid);
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if (gen < 3)
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mmio_size = 512*1024;
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else if (gen < 5)
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mmio_size = 512*1024;
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else
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mmio_size = 2*1024*1024;
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error = pci_device_map_range (pci_dev,
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pci_dev->regions[mmio_bar].base_addr,
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mmio_size,
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PCI_DEV_MAP_FLAG_WRITABLE,
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&igt_global_mmio);
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igt_fail_on_f(error != 0,
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"Couldn't map MMIO region\n");
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}
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static void
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release_forcewake_lock(int fd)
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{
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close(fd);
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}
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/**
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* intel_register_access_init:
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* @pci_dev: intel graphics pci device
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* @safe: use safe register access tables
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*
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* This initializes the new register access library, which supports forcewake
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* handling and also allows register access to be checked with an explicit
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* whitelist.
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*
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* It also initializes #igt_global_mmio like intel_mmio_use_pci_bar().
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*
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* @pci_dev can be obtained from intel_get_pci_device().
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*/
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int
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intel_register_access_init(struct pci_device *pci_dev, int safe, int fd)
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{
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int ret;
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/* after old API is deprecated, remove this */
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if (igt_global_mmio == NULL)
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intel_mmio_use_pci_bar(pci_dev);
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igt_assert(igt_global_mmio != NULL);
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if (mmio_data.inited)
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return -1;
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mmio_data.safe = (safe != 0 &&
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intel_gen(pci_dev->device_id) >= 4) ? true : false;
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mmio_data.i915_devid = pci_dev->device_id;
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if (mmio_data.safe)
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mmio_data.map = intel_get_register_map(mmio_data.i915_devid);
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/* Find where the forcewake lock is. Forcewake doesn't exist
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* gen < 6, but the debugfs should do the right things for us.
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*/
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ret = igt_open_forcewake_handle(fd);
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if (ret == -1)
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mmio_data.key = FAKEKEY;
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else
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mmio_data.key = ret;
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mmio_data.inited++;
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return 0;
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}
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static int
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intel_register_access_needs_wake(void)
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{
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return mmio_data.key != FAKEKEY;
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}
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/**
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* intel_register_access_needs_fakewake:
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*
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* Returns:
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* Non-zero when forcewake initialization failed.
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*/
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int intel_register_access_needs_fakewake(void)
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{
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return mmio_data.key == FAKEKEY;
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}
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/**
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* intel_register_access_fini:
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*
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* Clean up the register access helper initialized with
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* intel_register_access_init().
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*/
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void
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intel_register_access_fini(void)
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{
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if (mmio_data.key && intel_register_access_needs_wake())
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release_forcewake_lock(mmio_data.key);
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mmio_data.inited--;
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}
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/**
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* intel_register_read:
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* @reg: register offset
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*
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* 32-bit read of the register at @offset. This function only works when the new
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* register access helper is initialized with intel_register_access_init().
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*
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* Compared to INREG() it can do optional checking with the register access
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* white lists.
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*
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* Returns:
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* The value read from the register.
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*/
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uint32_t
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intel_register_read(uint32_t reg)
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{
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struct intel_register_range *range;
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uint32_t ret;
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igt_assert(mmio_data.inited);
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if (intel_gen(mmio_data.i915_devid) >= 6)
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igt_assert(mmio_data.key != -1);
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if (!mmio_data.safe)
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goto read_out;
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range = intel_get_register_range(mmio_data.map,
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reg,
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INTEL_RANGE_READ);
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if(!range) {
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igt_warn("Register read blocked for safety ""(*0x%08x)\n", reg);
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ret = 0xffffffff;
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goto out;
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}
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read_out:
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ret = *(volatile uint32_t *)((volatile char *)igt_global_mmio + reg);
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out:
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return ret;
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}
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/**
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* intel_register_write:
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* @reg: register offset
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* @val: value to write
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*
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* 32-bit write to the register at @offset. This function only works when the new
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* register access helper is initialized with intel_register_access_init().
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*
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* Compared to OUTREG() it can do optional checking with the register access
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* white lists.
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*/
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void
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intel_register_write(uint32_t reg, uint32_t val)
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{
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struct intel_register_range *range;
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igt_assert(mmio_data.inited);
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if (intel_gen(mmio_data.i915_devid) >= 6)
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igt_assert(mmio_data.key != -1);
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if (!mmio_data.safe)
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goto write_out;
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range = intel_get_register_range(mmio_data.map,
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reg,
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INTEL_RANGE_WRITE);
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igt_warn_on_f(!range,
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"Register write blocked for safety ""(*0x%08x = 0x%x)\n", reg, val);
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write_out:
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*(volatile uint32_t *)((volatile char *)igt_global_mmio + reg) = val;
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}
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/**
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* INREG:
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* @reg: register offset
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*
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* 32-bit read of the register at offset @reg. This function only works when the
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* new register access helper is initialized with intel_register_access_init().
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*
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* This function directly accesses the #igt_global_mmio without safety checks.
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*
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* Returns:
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* The value read from the register.
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*/
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uint32_t INREG(uint32_t reg)
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{
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return *(volatile uint32_t *)((volatile char *)igt_global_mmio + reg);
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}
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/**
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* INREG16:
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* @reg: register offset
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*
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* 16-bit read of the register at offset @reg. This function only works when the
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* new register access helper is initialized with intel_register_access_init().
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*
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* This function directly accesses the #igt_global_mmio without safety checks.
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*
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* Returns:
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* The value read from the register.
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*/
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uint16_t INREG16(uint32_t reg)
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{
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return *(volatile uint16_t *)((volatile char *)igt_global_mmio + reg);
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}
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/**
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* INREG8:
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* @reg: register offset
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*
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* 8-bit read of the register at offset @reg. This function only works when the
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* new register access helper is initialized with intel_register_access_init().
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*
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* This function directly accesses the #igt_global_mmio without safety checks.
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*
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* Returns:
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* The value read from the register.
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*/
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uint8_t INREG8(uint32_t reg)
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{
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return *((volatile uint8_t *)igt_global_mmio + reg);
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}
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/**
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* OUTREG:
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* @reg: register offset
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* @val: value to write
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*
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* 32-bit write of @val to the register at offset @reg. This function only works
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* when the new register access helper is initialized with
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* intel_register_access_init().
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*
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* This function directly accesses the #igt_global_mmio without safety checks.
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*/
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void OUTREG(uint32_t reg, uint32_t val)
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{
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*(volatile uint32_t *)((volatile char *)igt_global_mmio + reg) = val;
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}
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/**
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* OUTREG16:
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* @reg: register offset
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* @val: value to write
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*
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* 16-bit write of @val to the register at offset @reg. This function only works
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* when the new register access helper is initialized with
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* intel_register_access_init().
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*
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* This function directly accesses the #igt_global_mmio without safety checks.
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*/
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void OUTREG16(uint32_t reg, uint16_t val)
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{
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*(volatile uint16_t *)((volatile char *)igt_global_mmio + reg) = val;
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}
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/**
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* OUTREG8:
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* @reg: register offset
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* @val: value to write
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*
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* 8-bit write of @val to the register at offset @reg. This function only works
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* when the new register access helper is initialized with
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* intel_register_access_init().
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*
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* This function directly accesses the #igt_global_mmio without safety checks.
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*/
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void OUTREG8(uint32_t reg, uint8_t val)
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{
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*((volatile uint8_t *)igt_global_mmio + reg) = val;
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}
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