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692 lines
17 KiB
692 lines
17 KiB
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <time.h>
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#include "igt.h"
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#include "igt_x86.h"
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IGT_TEST_DESCRIPTION("Basic check of flushing after batches");
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#define UNCACHED 0
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#define COHERENT 1
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#define WC 2
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#define WRITE 4
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#define KERNEL 8
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#define SET_DOMAIN 16
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#define BEFORE 32
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#define INTERRUPTIBLE 64
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#define CMDPARSER 128
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#define BASIC 256
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#define MOVNT 512
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#if defined(__x86_64__) && !defined(__clang__)
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#pragma GCC push_options
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#pragma GCC target("sse4.1")
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#include <smmintrin.h>
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__attribute__((noinline))
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static uint32_t movnt(uint32_t *map, int i)
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{
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__m128i tmp;
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tmp = _mm_stream_load_si128((__m128i *)map + i/4);
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switch (i%4) { /* gcc! */
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default:
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case 0: return _mm_extract_epi32(tmp, 0);
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case 1: return _mm_extract_epi32(tmp, 1);
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case 2: return _mm_extract_epi32(tmp, 2);
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case 3: return _mm_extract_epi32(tmp, 3);
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}
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}
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static inline unsigned x86_64_features(void)
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{
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return igt_x86_features();
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}
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#pragma GCC pop_options
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#else
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static inline unsigned x86_64_features(void)
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{
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return 0;
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}
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static uint32_t movnt(uint32_t *map, int i)
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{
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igt_assert(!"reached");
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}
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#endif
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static void run(int fd, unsigned ring, int nchild, int timeout,
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unsigned flags)
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{
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const int gen = intel_gen(intel_get_drm_devid(fd));
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/* The crux of this testing is whether writes by the GPU are coherent
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* from the CPU.
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*
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* For example, using plain clflush (the simplest and most visible
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* in terms of function calls / syscalls) we have two tests which
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* perform:
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*
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* USER (0):
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* execbuf(map[i] = i);
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* sync();
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* clflush(&map[i]);
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* assert(map[i] == i);
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*
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* execbuf(map[i] = i ^ ~0);
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* sync();
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* clflush(&map[i]);
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* assert(map[i] == i ^ ~0);
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*
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* BEFORE:
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* clflush(&map[i]);
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* execbuf(map[i] = i);
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* sync();
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* assert(map[i] == i);
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*
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* clflush(&map[i]);
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* execbuf(map[i] = i ^ ~0);
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* sync();
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* assert(map[i] == i ^ ~0);
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*
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* The assertion here is that the cacheline invalidations are precise
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* and we have no speculative prefetch that can see the future map[i]
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* access and bring it ahead of the execution, or accidental cache
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* pollution by the kernel.
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*/
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igt_fork(child, nchild) {
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const uint32_t bbe = MI_BATCH_BUFFER_END;
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struct drm_i915_gem_exec_object2 obj[3];
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struct drm_i915_gem_relocation_entry reloc0[1024];
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struct drm_i915_gem_relocation_entry reloc1[1024];
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struct drm_i915_gem_execbuffer2 execbuf;
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unsigned long cycles = 0;
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bool snoop = false;
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uint32_t *ptr;
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uint32_t *map;
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int i;
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memset(obj, 0, sizeof(obj));
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obj[0].handle = gem_create(fd, 4096);
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obj[0].flags |= EXEC_OBJECT_WRITE;
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if (flags & WC) {
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igt_assert(flags & COHERENT);
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map = gem_mmap__wc(fd, obj[0].handle, 0, 4096, PROT_WRITE);
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gem_set_domain(fd, obj[0].handle,
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I915_GEM_DOMAIN_WC,
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I915_GEM_DOMAIN_WC);
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} else {
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snoop = flags & COHERENT;
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gem_set_caching(fd, obj[0].handle, snoop);
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map = gem_mmap__cpu(fd, obj[0].handle, 0, 4096, PROT_WRITE);
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gem_set_domain(fd, obj[0].handle,
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I915_GEM_DOMAIN_CPU,
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I915_GEM_DOMAIN_CPU);
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}
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for (i = 0; i < 1024; i++)
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map[i] = 0xabcdabcd;
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gem_set_domain(fd, obj[0].handle,
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I915_GEM_DOMAIN_WC,
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I915_GEM_DOMAIN_WC);
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/* Prepara a mappable binding to prevent pread mighrating */
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if (!snoop) {
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ptr = gem_mmap__gtt(fd, obj[0].handle, 4096, PROT_READ);
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igt_assert_eq_u32(ptr[0], 0xabcdabcd);
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munmap(ptr, 4096);
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}
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffers_ptr = to_user_pointer(obj);
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execbuf.buffer_count = 3;
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execbuf.flags = ring | (1 << 11) | (1<<12);
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if (gen < 6)
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execbuf.flags |= I915_EXEC_SECURE;
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obj[1].handle = gem_create(fd, 1024*64);
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obj[2].handle = gem_create(fd, 1024*64);
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gem_write(fd, obj[2].handle, 0, &bbe, sizeof(bbe));
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igt_require(__gem_execbuf(fd, &execbuf) == 0);
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obj[1].relocation_count = 1;
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obj[2].relocation_count = 1;
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ptr = gem_mmap__wc(fd, obj[1].handle, 0, 64*1024,
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PROT_WRITE | PROT_READ);
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gem_set_domain(fd, obj[1].handle,
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I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC);
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memset(reloc0, 0, sizeof(reloc0));
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for (i = 0; i < 1024; i++) {
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uint64_t offset;
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uint32_t *b = &ptr[16 * i];
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reloc0[i].presumed_offset = obj[0].offset;
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reloc0[i].offset = (b - ptr + 1) * sizeof(*ptr);
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reloc0[i].delta = i * sizeof(uint32_t);
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reloc0[i].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
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reloc0[i].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
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offset = obj[0].offset + reloc0[i].delta;
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*b++ = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
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if (gen >= 8) {
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*b++ = offset;
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*b++ = offset >> 32;
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} else if (gen >= 4) {
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*b++ = 0;
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*b++ = offset;
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reloc0[i].offset += sizeof(*ptr);
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} else {
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b[-1] -= 1;
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*b++ = offset;
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}
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*b++ = i;
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*b++ = MI_BATCH_BUFFER_END;
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}
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munmap(ptr, 64*1024);
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ptr = gem_mmap__wc(fd, obj[2].handle, 0, 64*1024,
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PROT_WRITE | PROT_READ);
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gem_set_domain(fd, obj[2].handle,
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I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC);
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memset(reloc1, 0, sizeof(reloc1));
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for (i = 0; i < 1024; i++) {
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uint64_t offset;
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uint32_t *b = &ptr[16 * i];
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reloc1[i].presumed_offset = obj[0].offset;
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reloc1[i].offset = (b - ptr + 1) * sizeof(*ptr);
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reloc1[i].delta = i * sizeof(uint32_t);
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reloc1[i].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
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reloc1[i].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
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offset = obj[0].offset + reloc1[i].delta;
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*b++ = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
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if (gen >= 8) {
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*b++ = offset;
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*b++ = offset >> 32;
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} else if (gen >= 4) {
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*b++ = 0;
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*b++ = offset;
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reloc1[i].offset += sizeof(*ptr);
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} else {
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b[-1] -= 1;
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*b++ = offset;
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}
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*b++ = i ^ 0xffffffff;
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*b++ = MI_BATCH_BUFFER_END;
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}
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munmap(ptr, 64*1024);
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igt_until_timeout(timeout) {
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bool xor = false;
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int idx = cycles++ % 1024;
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/* Inspect a different cacheline each iteration */
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i = 16 * (idx % 64) + (idx / 64);
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obj[1].relocs_ptr = to_user_pointer(&reloc0[i]);
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obj[2].relocs_ptr = to_user_pointer(&reloc1[i]);
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igt_assert_eq_u64(reloc0[i].presumed_offset, obj[0].offset);
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igt_assert_eq_u64(reloc1[i].presumed_offset, obj[0].offset);
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execbuf.batch_start_offset = 64*i;
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overwrite:
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if ((flags & BEFORE) &&
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!((flags & COHERENT) || gem_has_llc(fd)))
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igt_clflush_range(&map[i], sizeof(map[i]));
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execbuf.buffer_count = 2 + xor;
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gem_execbuf(fd, &execbuf);
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if (flags & SET_DOMAIN) {
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unsigned domain = flags & WC ? I915_GEM_DOMAIN_WC : I915_GEM_DOMAIN_CPU;
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igt_while_interruptible(flags & INTERRUPTIBLE)
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gem_set_domain(fd, obj[0].handle,
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domain, (flags & WRITE) ? domain : 0);
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if (xor)
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igt_assert_eq_u32(map[i], i ^ 0xffffffff);
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else
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igt_assert_eq_u32(map[i], i);
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if (flags & WRITE)
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map[i] = 0xdeadbeef;
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} else if (flags & KERNEL) {
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uint32_t val;
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igt_while_interruptible(flags & INTERRUPTIBLE)
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gem_read(fd, obj[0].handle,
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i*sizeof(uint32_t),
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&val, sizeof(val));
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if (xor)
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igt_assert_eq_u32(val, i ^ 0xffffffff);
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else
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igt_assert_eq_u32(val, i);
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if (flags & WRITE) {
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val = 0xdeadbeef;
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igt_while_interruptible(flags & INTERRUPTIBLE)
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gem_write(fd, obj[0].handle,
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i*sizeof(uint32_t),
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&val, sizeof(val));
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}
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} else if (flags & MOVNT) {
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uint32_t x;
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igt_while_interruptible(flags & INTERRUPTIBLE)
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gem_sync(fd, obj[0].handle);
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x = movnt(map, i);
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if (xor)
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igt_assert_eq_u32(x, i ^ 0xffffffff);
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else
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igt_assert_eq_u32(x, i);
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if (flags & WRITE)
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map[i] = 0xdeadbeef;
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} else {
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igt_while_interruptible(flags & INTERRUPTIBLE)
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gem_sync(fd, obj[0].handle);
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if (!(flags & (BEFORE | COHERENT)) &&
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!gem_has_llc(fd))
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igt_clflush_range(&map[i], sizeof(map[i]));
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if (xor)
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igt_assert_eq_u32(map[i], i ^ 0xffffffff);
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else
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igt_assert_eq_u32(map[i], i);
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if (flags & WRITE) {
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map[i] = 0xdeadbeef;
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if (!(flags & (COHERENT | BEFORE)))
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igt_clflush_range(&map[i], sizeof(map[i]));
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}
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}
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if (!xor) {
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xor= true;
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goto overwrite;
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}
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}
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igt_info("Child[%d]: %lu cycles\n", child, cycles);
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gem_close(fd, obj[2].handle);
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gem_close(fd, obj[1].handle);
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munmap(map, 4096);
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gem_close(fd, obj[0].handle);
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}
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igt_waitchildren();
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}
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enum batch_mode {
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BATCH_KERNEL,
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BATCH_USER,
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BATCH_CPU,
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BATCH_GTT,
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BATCH_WC,
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};
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static void batch(int fd, unsigned ring, int nchild, int timeout,
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enum batch_mode mode, unsigned flags)
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{
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const int gen = intel_gen(intel_get_drm_devid(fd));
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if (flags & CMDPARSER) {
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int cmdparser = -1;
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drm_i915_getparam_t gp;
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gp.param = I915_PARAM_CMD_PARSER_VERSION;
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gp.value = &cmdparser;
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drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
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igt_require(cmdparser > 0);
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}
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intel_detect_and_clear_missed_interrupts(fd);
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igt_fork(child, nchild) {
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const uint32_t bbe = MI_BATCH_BUFFER_END;
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struct drm_i915_gem_exec_object2 obj[2];
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struct drm_i915_gem_relocation_entry reloc;
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struct drm_i915_gem_execbuffer2 execbuf;
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unsigned long cycles = 0;
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uint32_t *ptr;
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uint32_t *map;
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int i;
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memset(obj, 0, sizeof(obj));
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obj[0].handle = gem_create(fd, 4096);
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obj[0].flags |= EXEC_OBJECT_WRITE;
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gem_set_caching(fd, obj[0].handle, !!(flags & COHERENT));
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map = gem_mmap__cpu(fd, obj[0].handle, 0, 4096, PROT_WRITE);
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gem_set_domain(fd, obj[0].handle,
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I915_GEM_DOMAIN_CPU,
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I915_GEM_DOMAIN_CPU);
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for (i = 0; i < 1024; i++)
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map[i] = 0xabcdabcd;
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffers_ptr = to_user_pointer(obj);
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execbuf.buffer_count = 2;
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execbuf.flags = ring | (1 << 11) | (1<<12);
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if (gen < 6)
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execbuf.flags |= I915_EXEC_SECURE;
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obj[1].handle = gem_create(fd, 64<<10);
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gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
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igt_require(__gem_execbuf(fd, &execbuf) == 0);
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obj[1].relocation_count = 1;
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obj[1].relocs_ptr = to_user_pointer(&reloc);
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switch (mode) {
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case BATCH_CPU:
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case BATCH_USER:
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ptr = gem_mmap__cpu(fd, obj[1].handle, 0, 64<<10,
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PROT_WRITE);
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break;
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case BATCH_WC:
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ptr = gem_mmap__wc(fd, obj[1].handle, 0, 64<<10,
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PROT_WRITE);
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break;
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case BATCH_GTT:
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ptr = gem_mmap__gtt(fd, obj[1].handle, 64<<10,
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PROT_WRITE);
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break;
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case BATCH_KERNEL:
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ptr = mmap(0, 64<<10, PROT_WRITE,
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MAP_PRIVATE | MAP_ANON, -1, 0);
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break;
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default:
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igt_assert(!"reachable");
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ptr = NULL;
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break;
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}
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memset(&reloc, 0, sizeof(reloc));
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reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
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reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
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igt_until_timeout(timeout) {
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execbuf.batch_start_offset = 0;
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reloc.offset = sizeof(uint32_t);
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if (gen >= 4 && gen < 8)
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reloc.offset += sizeof(uint32_t);
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for (i = 0; i < 1024; i++) {
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uint64_t offset;
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uint32_t *start = &ptr[execbuf.batch_start_offset/sizeof(*start)];
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uint32_t *b = start;
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switch (mode) {
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case BATCH_CPU:
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gem_set_domain(fd, obj[1].handle,
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I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
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break;
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case BATCH_WC:
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gem_set_domain(fd, obj[1].handle,
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I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC);
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break;
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case BATCH_GTT:
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gem_set_domain(fd, obj[1].handle,
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I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
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break;
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case BATCH_USER:
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case BATCH_KERNEL:
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break;
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}
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reloc.presumed_offset = obj[0].offset;
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reloc.delta = i * sizeof(uint32_t);
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offset = reloc.presumed_offset + reloc.delta;
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*b++ = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
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if (gen >= 8) {
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*b++ = offset;
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*b++ = offset >> 32;
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} else if (gen >= 4) {
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*b++ = 0;
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*b++ = offset;
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} else {
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b[-1] -= 1;
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*b++ = offset;
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}
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*b++ = cycles + i;
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*b++ = MI_BATCH_BUFFER_END;
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if (flags & CMDPARSER) {
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execbuf.batch_len =
|
|
(b - start) * sizeof(uint32_t);
|
|
if (execbuf.batch_len & 4)
|
|
execbuf.batch_len += 4;
|
|
}
|
|
|
|
switch (mode) {
|
|
case BATCH_KERNEL:
|
|
gem_write(fd, obj[1].handle,
|
|
execbuf.batch_start_offset,
|
|
start, (b - start) * sizeof(uint32_t));
|
|
break;
|
|
|
|
case BATCH_USER:
|
|
if (!gem_has_llc(fd))
|
|
igt_clflush_range(start,
|
|
(b - start) * sizeof(uint32_t));
|
|
break;
|
|
|
|
case BATCH_CPU:
|
|
case BATCH_GTT:
|
|
case BATCH_WC:
|
|
break;
|
|
}
|
|
gem_execbuf(fd, &execbuf);
|
|
|
|
execbuf.batch_start_offset += 64;
|
|
reloc.offset += 64;
|
|
}
|
|
|
|
if (!(flags & COHERENT)) {
|
|
gem_set_domain(fd, obj[0].handle,
|
|
I915_GEM_DOMAIN_CPU,
|
|
I915_GEM_DOMAIN_CPU);
|
|
} else
|
|
gem_sync(fd, obj[0].handle);
|
|
for (i = 0; i < 1024; i++) {
|
|
igt_assert_eq_u32(map[i], cycles + i);
|
|
map[i] = 0xabcdabcd ^ cycles;
|
|
}
|
|
cycles += 1024;
|
|
|
|
if (mode == BATCH_USER)
|
|
gem_sync(fd, obj[1].handle);
|
|
}
|
|
igt_info("Child[%d]: %lu cycles\n", child, cycles);
|
|
|
|
munmap(ptr, 64<<10);
|
|
gem_close(fd, obj[1].handle);
|
|
|
|
munmap(map, 4096);
|
|
gem_close(fd, obj[0].handle);
|
|
}
|
|
igt_waitchildren();
|
|
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
|
|
}
|
|
|
|
static const char *yesno(bool x)
|
|
{
|
|
return x ? "yes" : "no";
|
|
}
|
|
|
|
igt_main
|
|
{
|
|
const struct intel_execution_engine *e;
|
|
const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
|
|
const struct batch {
|
|
const char *name;
|
|
unsigned mode;
|
|
} batches[] = {
|
|
{ "kernel", BATCH_KERNEL },
|
|
{ "user", BATCH_USER },
|
|
{ "cpu", BATCH_CPU },
|
|
{ "gtt", BATCH_GTT },
|
|
{ "wc", BATCH_WC },
|
|
{ NULL }
|
|
};
|
|
const struct mode {
|
|
const char *name;
|
|
unsigned flags;
|
|
} modes[] = {
|
|
{ "ro", BASIC },
|
|
{ "rw", BASIC | WRITE },
|
|
{ "ro-before", BEFORE },
|
|
{ "rw-before", BEFORE | WRITE },
|
|
{ "pro", BASIC | KERNEL },
|
|
{ "prw", BASIC | KERNEL | WRITE },
|
|
{ "set", BASIC | SET_DOMAIN | WRITE },
|
|
{ NULL }
|
|
};
|
|
unsigned cpu = x86_64_features();
|
|
int fd = -1;
|
|
|
|
igt_fixture {
|
|
igt_require(igt_setup_clflush());
|
|
fd = drm_open_driver(DRIVER_INTEL);
|
|
igt_require_gem(fd);
|
|
gem_require_mmap_wc(fd);
|
|
igt_require(gem_can_store_dword(fd, 0));
|
|
igt_info("Has LLC? %s\n", yesno(gem_has_llc(fd)));
|
|
|
|
if (cpu) {
|
|
char str[1024];
|
|
|
|
igt_info("CPU features: %s\n",
|
|
igt_x86_features_to_string(cpu, str));
|
|
}
|
|
|
|
igt_fork_hang_detector(fd);
|
|
}
|
|
|
|
for (e = intel_execution_engines; e->name; e++) igt_subtest_group {
|
|
unsigned ring = e->exec_id | e->flags;
|
|
unsigned timeout = 5 + 120*!!e->exec_id;
|
|
|
|
igt_fixture {
|
|
gem_require_ring(fd, ring);
|
|
igt_require(gem_can_store_dword(fd, ring));
|
|
}
|
|
|
|
for (const struct batch *b = batches; b->name; b++) {
|
|
igt_subtest_f("%sbatch-%s-%s-uc",
|
|
b == batches && e->exec_id == 0 ? "basic-" : "",
|
|
b->name,
|
|
e->name)
|
|
batch(fd, ring, ncpus, timeout, b->mode, 0);
|
|
igt_subtest_f("%sbatch-%s-%s-wb",
|
|
b == batches && e->exec_id == 0 ? "basic-" : "",
|
|
b->name,
|
|
e->name)
|
|
batch(fd, ring, ncpus, timeout, b->mode, COHERENT);
|
|
igt_subtest_f("%sbatch-%s-%s-cmd",
|
|
b == batches && e->exec_id == 0 ? "basic-" : "",
|
|
b->name,
|
|
e->name)
|
|
batch(fd, ring, ncpus, timeout, b->mode,
|
|
COHERENT | CMDPARSER);
|
|
}
|
|
|
|
for (const struct mode *m = modes; m->name; m++) {
|
|
igt_subtest_f("%suc-%s-%s",
|
|
(m->flags & BASIC && e->exec_id == 0) ? "basic-" : "",
|
|
m->name,
|
|
e->name)
|
|
run(fd, ring, ncpus, timeout,
|
|
UNCACHED | m->flags);
|
|
|
|
igt_subtest_f("uc-%s-%s-interruptible",
|
|
m->name,
|
|
e->name)
|
|
run(fd, ring, ncpus, timeout,
|
|
UNCACHED | m->flags | INTERRUPTIBLE);
|
|
|
|
igt_subtest_f("%swb-%s-%s",
|
|
e->exec_id == 0 ? "basic-" : "",
|
|
m->name,
|
|
e->name)
|
|
run(fd, ring, ncpus, timeout,
|
|
COHERENT | m->flags);
|
|
|
|
igt_subtest_f("wb-%s-%s-interruptible",
|
|
m->name,
|
|
e->name)
|
|
run(fd, ring, ncpus, timeout,
|
|
COHERENT | m->flags | INTERRUPTIBLE);
|
|
|
|
igt_subtest_f("wc-%s-%s",
|
|
m->name,
|
|
e->name)
|
|
run(fd, ring, ncpus, timeout,
|
|
COHERENT | WC | m->flags);
|
|
|
|
igt_subtest_f("wc-%s-%s-interruptible",
|
|
m->name,
|
|
e->name)
|
|
run(fd, ring, ncpus, timeout,
|
|
COHERENT | WC | m->flags | INTERRUPTIBLE);
|
|
|
|
igt_subtest_f("stream-%s-%s",
|
|
m->name,
|
|
e->name) {
|
|
igt_require(cpu & SSE4_1);
|
|
run(fd, ring, ncpus, timeout,
|
|
MOVNT | COHERENT | WC | m->flags);
|
|
}
|
|
|
|
igt_subtest_f("stream-%s-%s-interruptible",
|
|
m->name,
|
|
e->name) {
|
|
igt_require(cpu & SSE4_1);
|
|
run(fd, ring, ncpus, timeout,
|
|
MOVNT | COHERENT | WC | m->flags | INTERRUPTIBLE);
|
|
}
|
|
}
|
|
}
|
|
|
|
igt_fixture {
|
|
igt_stop_hang_detector();
|
|
close(fd);
|
|
}
|
|
}
|