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235 lines
6.1 KiB
235 lines
6.1 KiB
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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*
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*/
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/** @file gem_request_retire
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*
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* Collection of tests targeting request retirement code paths.
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*/
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#include "igt.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/time.h>
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#include <sys/mman.h>
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#include <signal.h>
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#include <pthread.h>
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#include <time.h>
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#include "drm.h"
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#include "i915_drm.h"
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#include "intel_bufmgr.h"
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IGT_TEST_DESCRIPTION("Collection of tests targeting request retirement code"
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" paths.");
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#define WIDTH 4096
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#define HEIGHT 4096
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#define BO_SIZE (WIDTH * HEIGHT * sizeof(uint32_t))
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static uint32_t
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blit(int fd, uint32_t dst, uint32_t src, uint32_t ctx_id)
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{
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const unsigned int copies = 1000;
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uint32_t batch[12 * copies + 5];
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struct drm_i915_gem_relocation_entry reloc[2 * copies];
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struct drm_i915_gem_exec_object2 obj[3];
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struct drm_i915_gem_execbuffer2 exec;
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uint32_t handle;
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unsigned int i = 0, j, r = 0;
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for (j = 0; j < copies; j++) {
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reloc[r].target_handle = dst;
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reloc[r].delta = 0;
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reloc[r].offset = (i + 4) * sizeof(uint32_t);
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reloc[r].presumed_offset = 0;
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reloc[r].read_domains = I915_GEM_DOMAIN_RENDER;
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reloc[r].write_domain = I915_GEM_DOMAIN_RENDER;
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r++;
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reloc[r].target_handle = src;
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reloc[r].delta = 0;
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reloc[r].offset = (i + 7) * sizeof(uint32_t);
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if (intel_gen(intel_get_drm_devid(fd)) >= 8)
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reloc[r].offset += sizeof(uint32_t);
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reloc[r].presumed_offset = 0;
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reloc[r].read_domains = I915_GEM_DOMAIN_RENDER;
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reloc[r].write_domain = 0;
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r++;
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batch[i++] = XY_SRC_COPY_BLT_CMD |
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XY_SRC_COPY_BLT_WRITE_ALPHA |
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XY_SRC_COPY_BLT_WRITE_RGB;
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if (intel_gen(intel_get_drm_devid(fd)) >= 8)
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batch[i - 1] |= 8;
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else
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batch[i - 1] |= 6;
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batch[i++] = (3 << 24) | /* 32 bits */
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(0xcc << 16) | /* copy ROP */
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WIDTH*4;
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batch[i++] = 0; /* dst x1,y1 */
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batch[i++] = (HEIGHT << 16) | WIDTH; /* dst x2,y2 */
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batch[i++] = 0; /* dst reloc */
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if (intel_gen(intel_get_drm_devid(fd)) >= 8)
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batch[i++] = 0;
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batch[i++] = 0; /* src x1,y1 */
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batch[i++] = WIDTH*4;
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batch[i++] = 0; /* src reloc */
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if (intel_gen(intel_get_drm_devid(fd)) >= 8)
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batch[i++] = 0;
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}
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batch[i++] = MI_BATCH_BUFFER_END;
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while (i % 4)
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batch[i++] = MI_NOOP;
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handle = gem_create(fd, sizeof(batch));
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gem_write(fd, handle, 0, batch, sizeof(batch));
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memset(obj, 0, sizeof(obj));
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memset(&exec, 0, sizeof(exec));
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obj[exec.buffer_count++].handle = dst;
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if (src != dst)
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obj[exec.buffer_count++].handle = src;
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obj[exec.buffer_count].handle = handle;
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obj[exec.buffer_count].relocation_count = 2 * copies;
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obj[exec.buffer_count].relocs_ptr = to_user_pointer(reloc);
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exec.buffer_count++;
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exec.buffers_ptr = to_user_pointer(obj);
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exec.batch_len = i * sizeof(uint32_t);
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exec.flags = I915_EXEC_BLT;
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i915_execbuffer2_set_context_id(exec, ctx_id);
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gem_execbuf(fd, &exec);
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return handle;
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}
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static uint32_t
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noop(int fd, uint32_t src, uint32_t ctx_id)
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{
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uint32_t batch[4];
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struct drm_i915_gem_exec_object2 obj[2];
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struct drm_i915_gem_execbuffer2 exec;
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uint32_t handle;
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unsigned int i = 0;
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batch[i++] = MI_NOOP;
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batch[i++] = MI_BATCH_BUFFER_END;
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batch[i++] = MI_NOOP;
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batch[i++] = MI_NOOP;
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handle = gem_create(fd, 4096);
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gem_write(fd, handle, 0, batch, sizeof(batch));
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memset(obj, 0, sizeof(obj));
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memset(&exec, 0, sizeof(exec));
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obj[exec.buffer_count++].handle = src;
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obj[exec.buffer_count].handle = handle;
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obj[exec.buffer_count].relocation_count = 0;
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obj[exec.buffer_count].relocs_ptr = to_user_pointer(0);
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exec.buffer_count++;
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exec.buffers_ptr = to_user_pointer(obj);
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exec.batch_len = i * sizeof(uint32_t);
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exec.flags = I915_EXEC_RENDER;
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i915_execbuffer2_set_context_id(exec, ctx_id);
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gem_execbuf(fd, &exec);
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return handle;
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}
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/*
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* A single bo is operated from batchbuffers submitted from two contexts and on
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* different rings.
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* One execbuf finishes way ahead of the other at which point the respective
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* context is destroyed.
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*/
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static void
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test_retire_vma_not_inactive(int fd)
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{
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uint32_t ctx_id;
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uint32_t src, dst;
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uint32_t blit_bb, noop_bb;
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igt_require(HAS_BLT_RING(intel_get_drm_devid(fd)));
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ctx_id = gem_context_create(fd);
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/* Create some bos batch buffers will operate on. */
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src = gem_create(fd, BO_SIZE);
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dst = gem_create(fd, BO_SIZE);
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/* Submit a long running batch. */
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blit_bb = blit(fd, dst, src, 0);
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/* Submit a quick batch referencing the same object. */
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noop_bb = noop(fd, src, ctx_id);
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/* Wait for the quick batch to complete. */
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gem_sync(fd, noop_bb);
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gem_close(fd, noop_bb);
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/* Now destroy the context in which the quick batch was submitted. */
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gem_context_destroy(fd, ctx_id);
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/* Wait for the slow batch to finish and clean up. */
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gem_sync(fd, blit_bb);
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gem_close(fd, blit_bb);
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gem_close(fd, src);
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gem_close(fd, dst);
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}
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int fd;
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igt_main
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{
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igt_fixture {
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fd = drm_open_driver(DRIVER_INTEL);
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igt_require_gem(fd);
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gem_require_contexts(fd);
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}
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igt_subtest("retire-vma-not-inactive")
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test_retire_vma_not_inactive(fd);
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}
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