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135 lines
3.6 KiB
135 lines
3.6 KiB
// Copyright (c) 2012 The Chromium Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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#include "base/cpu.h"
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#include "base/stl_util.h"
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#include "build/build_config.h"
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#include "testing/gtest/include/gtest/gtest.h"
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#if _MSC_VER >= 1700
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// C4752: found Intel(R) Advanced Vector Extensions; consider using /arch:AVX.
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#pragma warning(disable: 4752)
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#endif
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// Tests whether we can run extended instructions represented by the CPU
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// information. This test actually executes some extended instructions (such as
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// MMX, SSE, etc.) supported by the CPU and sees we can run them without
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// "undefined instruction" exceptions. That is, this test succeeds when this
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// test finishes without a crash.
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TEST(CPU, RunExtendedInstructions) {
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#if defined(ARCH_CPU_X86_FAMILY)
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// Retrieve the CPU information.
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base::CPU cpu;
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ASSERT_TRUE(cpu.has_mmx());
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ASSERT_TRUE(cpu.has_sse());
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ASSERT_TRUE(cpu.has_sse2());
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// GCC and clang instruction test.
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#if defined(COMPILER_GCC)
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// Execute an MMX instruction.
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__asm__ __volatile__("emms\n" : : : "mm0");
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// Execute an SSE instruction.
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__asm__ __volatile__("xorps %%xmm0, %%xmm0\n" : : : "xmm0");
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// Execute an SSE 2 instruction.
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__asm__ __volatile__("psrldq $0, %%xmm0\n" : : : "xmm0");
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if (cpu.has_sse3()) {
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// Execute an SSE 3 instruction.
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__asm__ __volatile__("addsubpd %%xmm0, %%xmm0\n" : : : "xmm0");
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}
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if (cpu.has_ssse3()) {
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// Execute a Supplimental SSE 3 instruction.
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__asm__ __volatile__("psignb %%xmm0, %%xmm0\n" : : : "xmm0");
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}
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if (cpu.has_sse41()) {
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// Execute an SSE 4.1 instruction.
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__asm__ __volatile__("pmuldq %%xmm0, %%xmm0\n" : : : "xmm0");
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}
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if (cpu.has_sse42()) {
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// Execute an SSE 4.2 instruction.
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__asm__ __volatile__("crc32 %%eax, %%eax\n" : : : "eax");
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}
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if (cpu.has_popcnt()) {
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// Execute a POPCNT instruction.
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__asm__ __volatile__("popcnt %%eax, %%eax\n" : : : "eax");
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}
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if (cpu.has_avx()) {
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// Execute an AVX instruction.
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__asm__ __volatile__("vzeroupper\n" : : : "xmm0");
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}
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if (cpu.has_avx2()) {
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// Execute an AVX 2 instruction.
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__asm__ __volatile__("vpunpcklbw %%ymm0, %%ymm0, %%ymm0\n" : : : "xmm0");
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}
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// Visual C 32 bit and ClangCL 32/64 bit test.
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#elif defined(COMPILER_MSVC) && (defined(ARCH_CPU_32_BITS) || \
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(defined(ARCH_CPU_64_BITS) && defined(__clang__)))
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// Execute an MMX instruction.
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__asm emms;
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// Execute an SSE instruction.
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__asm xorps xmm0, xmm0;
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// Execute an SSE 2 instruction.
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__asm psrldq xmm0, 0;
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if (cpu.has_sse3()) {
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// Execute an SSE 3 instruction.
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__asm addsubpd xmm0, xmm0;
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}
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if (cpu.has_ssse3()) {
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// Execute a Supplimental SSE 3 instruction.
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__asm psignb xmm0, xmm0;
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}
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if (cpu.has_sse41()) {
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// Execute an SSE 4.1 instruction.
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__asm pmuldq xmm0, xmm0;
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}
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if (cpu.has_sse42()) {
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// Execute an SSE 4.2 instruction.
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__asm crc32 eax, eax;
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}
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if (cpu.has_popcnt()) {
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// Execute a POPCNT instruction.
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__asm popcnt eax, eax;
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}
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// Visual C 2012 required for AVX.
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#if _MSC_VER >= 1700
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if (cpu.has_avx()) {
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// Execute an AVX instruction.
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__asm vzeroupper;
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}
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if (cpu.has_avx2()) {
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// Execute an AVX 2 instruction.
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__asm vpunpcklbw ymm0, ymm0, ymm0
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}
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#endif // _MSC_VER >= 1700
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#endif // defined(COMPILER_GCC)
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#endif // defined(ARCH_CPU_X86_FAMILY)
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}
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// For https://crbug.com/249713
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TEST(CPU, BrandAndVendorContainsNoNUL) {
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base::CPU cpu;
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EXPECT_FALSE(base::ContainsValue(cpu.cpu_brand(), '\0'));
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EXPECT_FALSE(base::ContainsValue(cpu.vendor_name(), '\0'));
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}
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