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238 lines
7.9 KiB
238 lines
7.9 KiB
///*****************************************************************************
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//*
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//* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
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//*
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//* Licensed under the Apache License, Version 2.0 (the "License");
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//* you may not use this file except in compliance with the License.
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//* You may obtain a copy of the License at:
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//*
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//* http://www.apache.org/licenses/LICENSE-2.0
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//*
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//* Unless required by applicable law or agreed to in writing, software
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//* distributed under the License is distributed on an "AS IS" BASIS,
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//* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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//* See the License for the specific language governing permissions and
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//* limitations under the License.
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//*
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//*****************************************************************************/
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///**
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// *******************************************************************************
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// * @file
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// * ihevc_itrans_recon_4x4_neon.s
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// *
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// * @brief
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// * contains function definitions for single stage inverse transform
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// *
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// * @author
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// * naveen sr
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// *
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// * @par list of functions:
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// * - ihevc_itrans_recon_4x4()
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// *
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// * @remarks
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// * none
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// *
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// *******************************************************************************
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//*/
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// /**
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// *******************************************************************************
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// *
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// * @brief
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// * this function performs inverse transform and reconstruction for 4x4
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// * input block
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// *
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// * @par description:
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// * performs inverse transform and adds the prediction data and clips output
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// * to 8 bit
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// *
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// * @param[in] pi2_src
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// * input 4x4 coefficients
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// *
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// * @param[in] pi2_tmp
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// * temporary 4x4 buffer for storing inverse
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// *
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// * transform
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// * 1st stage output
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// *
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// * @param[in] pu1_pred
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// * prediction 4x4 block
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// *
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// * @param[out] pu1_dst
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// * output 4x4 block
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// *
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// * @param[in] src_strd
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// * input stride
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// *
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// * @param[in] pred_strd
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// * prediction stride
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// *
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// * @param[in] dst_strd
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// * output stride
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// *
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// * @param[in] shift
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// * output shift
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// *
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// * @param[in] zero_cols
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// * zero columns in pi2_src
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// *
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// * @returns void
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// *
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// * @remarks
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// * none
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// *
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// *******************************************************************************
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// */
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//void ihevc_itrans_recon_4x4(word16 *pi2_src,
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// word16 *pi2_tmp,
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// uword8 *pu1_pred,
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// uword8 *pu1_dst,
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// word32 src_strd,
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// word32 pred_strd,
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// word32 dst_strd,
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// word32 zero_cols)
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//**************variables vs registers*************************
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// x0 => *pi2_src
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// x1 => *pi2_tmp
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// x2 => *pu1_pred
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// x3 => *pu1_dst
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// x4 => src_strd
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// x5 => pred_strd
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// x6 => dst_strd
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// x7 => zero_cols
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.text
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.align 4
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.include "ihevc_neon_macros.s"
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.set shift_stage1_idct , 7
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.set shift_stage2_idct , 12
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.globl ihevc_itrans_recon_4x4_av8
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.extern g_ai2_ihevc_trans_4_transpose
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.type ihevc_itrans_recon_4x4_av8, %function
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ihevc_itrans_recon_4x4_av8:
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// stmfd sp!, {x4-x12, x14} //stack stores the values of the arguments
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stp x19, x20,[sp,#-16]!
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adrp x8, :got:g_ai2_ihevc_trans_4_transpose
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ldr x8, [x8, #:got_lo12:g_ai2_ihevc_trans_4_transpose]
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add x4,x4,x4 // src_strd in terms of word16
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add x9,x0,x4 // pi2_src[0] + src_strd
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ld1 {v4.4h},[x8] //loading first row of g_ai2_ihevc_trans_4_transpose
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// d4 = {36,64,83,64}
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//index = 3 2 1 0
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add x10,x9,x4, lsl #1 // 3*src_strd
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add x4,x4,x4
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ld1 {v1.4h},[x9] //loading pi2_src 2nd row
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ld1 {v3.4h},[x10] //loading pi2_src 4th row
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ld1 {v0.4h},[x0],x4 //loading pi2_src 1st row
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ld1 {v2.4h},[x0],x4 //loading pi2_src 3rd row
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// first stage computation starts
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smull v6.4s, v1.4h, v4.h[1] //83 * pi2_src[1]
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smlal v6.4s, v3.4h, v4.h[3] //o[0] = 83 * pi2_src[1] + 36 * pi2_src[3]
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smull v5.4s, v1.4h, v4.h[3] //36 * pi2_src[1]
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ld1 {v22.s}[0],[x2],x5
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smlsl v5.4s, v3.4h, v4.h[1] //o[1] = 36 * pi2_src[1] - 83 * pi2_src[3]
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saddl v7.4s, v0.4h, v2.4h //pi2_src[0] + pi2_src[2]
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ssubl v17.4s, v0.4h, v2.4h //pi2_src[0] - pi2_src[2]
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shl v7.4s, v7.4s,#6 //e[0] = 64*(pi2_src[0] + pi2_src[2])
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shl v17.4s, v17.4s,#6 //e[1] = 64*(pi2_src[0] - pi2_src[2])
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add v19.4s, v7.4s , v6.4s //((e[0] + o[0] )
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add v16.4s, v17.4s , v5.4s //((e[1] + o[1])
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sub v18.4s, v17.4s , v5.4s //((e[1] - o[1])
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sub v20.4s, v7.4s , v6.4s //((e[0] - o[0])
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sqrshrn v28.4h, v19.4s,#shift_stage1_idct //pi2_out[0] = clip_s16((e[0] + o[0] + add)>>shift) )
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sqrshrn v29.4h, v16.4s,#shift_stage1_idct //pi2_out[1] = clip_s16((e[1] + o[1] + add)>>shift) )
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sqrshrn v30.4h, v18.4s,#shift_stage1_idct //pi2_out[2] = clip_s16((e[0] - o[0] + add)>>shift) )
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sqrshrn v31.4h, v20.4s,#shift_stage1_idct //pi2_out[3] = clip_s16((e[0] - o[0] + add)>>shift) )
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trn1 v24.4h, v28.4h, v29.4h
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trn2 v25.4h, v28.4h, v29.4h
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trn1 v26.4h, v30.4h, v31.4h
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trn2 v27.4h, v30.4h, v31.4h
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trn1 v0.2s, v24.2s, v26.2s
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trn2 v2.2s, v24.2s, v26.2s
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trn1 v1.2s, v25.2s, v27.2s
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trn2 v3.2s, v25.2s, v27.2s
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// first stage ends
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// output in d0,d1,d2,d3
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// second stage starts
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smull v6.4s, v1.4h, v4.h[1] //83 * pi2_src[1]
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ld1 {v22.s}[1],[x2],x5
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smlal v6.4s, v3.4h, v4.h[3] //o[0] = 83 * pi2_src[1] + 36 * pi2_src[3]
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smull v5.4s, v1.4h, v4.h[3] //36 * pi2_src[1]
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smlsl v5.4s, v3.4h, v4.h[1] //o[1] = 36 * pi2_src[1] - 83 * pi2_src[3]
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ld1 {v23.s}[0],[x2],x5
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saddl v7.4s, v0.4h, v2.4h //pi2_src[0] + pi2_src[2]
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ssubl v17.4s, v0.4h, v2.4h //pi2_src[0] - pi2_src[2]
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shl v7.4s, v7.4s,#6 //e[0] = 64*(pi2_src[0] + pi2_src[2])
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shl v17.4s, v17.4s,#6 //e[1] = 64*(pi2_src[0] - pi2_src[2])
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add v19.4s, v7.4s , v6.4s //((e[0] + o[0] )
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add v16.4s, v17.4s , v5.4s //((e[1] + o[1])
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sub v18.4s, v17.4s , v5.4s //((e[1] - o[1])
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sub v20.4s, v7.4s , v6.4s //((e[0] - o[0])
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sqrshrn v28.4h, v19.4s,#shift_stage2_idct //pi2_out[0] = clip_s16((e[0] + o[0] + add)>>shift) )
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sqrshrn v29.4h, v16.4s,#shift_stage2_idct //pi2_out[1] = clip_s16((e[1] + o[1] + add)>>shift) )
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sqrshrn v30.4h, v18.4s,#shift_stage2_idct //pi2_out[2] = clip_s16((e[0] - o[0] + add)>>shift) )
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sqrshrn v31.4h, v20.4s,#shift_stage2_idct //pi2_out[3] = clip_s16((e[0] - o[0] + add)>>shift) )
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ld1 {v23.s}[1],[x2],x5
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trn1 v24.4h, v28.4h, v29.4h
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trn2 v25.4h, v28.4h, v29.4h
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trn1 v26.4h, v30.4h, v31.4h
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trn2 v27.4h, v30.4h, v31.4h
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trn1 v0.2s, v24.2s, v26.2s
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trn2 v2.2s, v24.2s, v26.2s
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trn1 v1.2s, v25.2s, v27.2s
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trn2 v3.2s, v25.2s, v27.2s
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// second stage ends
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// output in d0,d1,d2,d3
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// second stage computation ends
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// loading pred
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mov v0.d[1],v1.d[0]
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mov v2.d[1],v3.d[0]
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uaddw v0.8h, v0.8h , v22.8b // pi2_out(16bit) + pu1_pred(8bit)
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uaddw v2.8h, v2.8h , v23.8b // pi2_out(16bit) + pu1_pred(8bit)
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sqxtun v0.8b, v0.8h // clip_u8(pi2_out(16bit) + pu1_pred(8bit))
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sqxtun v1.8b, v2.8h // clip_u8(pi2_out(16bit) + pu1_pred(8bit))
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// storing destination
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st1 {v0.s}[0],[x3],x6
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st1 {v0.s}[1],[x3],x6
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st1 {v1.s}[0],[x3],x6
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st1 {v1.s}[1],[x3],x6
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// ldmfd sp!,{x4-x12,x15} //reload the registers from sp
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ldp x19, x20,[sp],#16
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ret
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