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673 lines
22 KiB
673 lines
22 KiB
//===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains support for writing dwarf debug info into asm files.
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//
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//===----------------------------------------------------------------------===//
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#include "DwarfExpression.h"
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#include "DwarfCompileUnit.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/SmallBitVector.h"
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#include "llvm/BinaryFormat/Dwarf.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <algorithm>
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using namespace llvm;
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#define DEBUG_TYPE "dwarfdebug"
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void DwarfExpression::emitConstu(uint64_t Value) {
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if (Value < 32)
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emitOp(dwarf::DW_OP_lit0 + Value);
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else if (Value == std::numeric_limits<uint64_t>::max()) {
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// Only do this for 64-bit values as the DWARF expression stack uses
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// target-address-size values.
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emitOp(dwarf::DW_OP_lit0);
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emitOp(dwarf::DW_OP_not);
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} else {
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emitOp(dwarf::DW_OP_constu);
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emitUnsigned(Value);
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}
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}
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void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
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assert(DwarfReg >= 0 && "invalid negative dwarf register number");
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assert((isUnknownLocation() || isRegisterLocation()) &&
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"location description already locked down");
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LocationKind = Register;
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if (DwarfReg < 32) {
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emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
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} else {
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emitOp(dwarf::DW_OP_regx, Comment);
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emitUnsigned(DwarfReg);
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}
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}
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void DwarfExpression::addBReg(int DwarfReg, int Offset) {
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assert(DwarfReg >= 0 && "invalid negative dwarf register number");
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assert(!isRegisterLocation() && "location description already locked down");
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if (DwarfReg < 32) {
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emitOp(dwarf::DW_OP_breg0 + DwarfReg);
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} else {
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emitOp(dwarf::DW_OP_bregx);
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emitUnsigned(DwarfReg);
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}
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emitSigned(Offset);
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}
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void DwarfExpression::addFBReg(int Offset) {
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emitOp(dwarf::DW_OP_fbreg);
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emitSigned(Offset);
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}
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void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
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if (!SizeInBits)
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return;
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const unsigned SizeOfByte = 8;
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if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
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emitOp(dwarf::DW_OP_bit_piece);
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emitUnsigned(SizeInBits);
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emitUnsigned(OffsetInBits);
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} else {
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emitOp(dwarf::DW_OP_piece);
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unsigned ByteSize = SizeInBits / SizeOfByte;
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emitUnsigned(ByteSize);
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}
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this->OffsetInBits += SizeInBits;
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}
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void DwarfExpression::addShr(unsigned ShiftBy) {
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emitConstu(ShiftBy);
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emitOp(dwarf::DW_OP_shr);
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}
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void DwarfExpression::addAnd(unsigned Mask) {
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emitConstu(Mask);
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emitOp(dwarf::DW_OP_and);
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}
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bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
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llvm::Register MachineReg,
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unsigned MaxSize) {
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if (!llvm::Register::isPhysicalRegister(MachineReg)) {
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if (isFrameRegister(TRI, MachineReg)) {
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DwarfRegs.push_back(Register::createRegister(-1, nullptr));
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return true;
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}
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return false;
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}
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int Reg = TRI.getDwarfRegNum(MachineReg, false);
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// If this is a valid register number, emit it.
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if (Reg >= 0) {
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DwarfRegs.push_back(Register::createRegister(Reg, nullptr));
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return true;
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}
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// Walk up the super-register chain until we find a valid number.
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// For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
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for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
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Reg = TRI.getDwarfRegNum(*SR, false);
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if (Reg >= 0) {
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unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
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unsigned Size = TRI.getSubRegIdxSize(Idx);
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unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
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DwarfRegs.push_back(Register::createRegister(Reg, "super-register"));
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// Use a DW_OP_bit_piece to describe the sub-register.
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setSubRegisterPiece(Size, RegOffset);
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return true;
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}
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}
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// Otherwise, attempt to find a covering set of sub-register numbers.
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// For example, Q0 on ARM is a composition of D0+D1.
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unsigned CurPos = 0;
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// The size of the register in bits.
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const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
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unsigned RegSize = TRI.getRegSizeInBits(*RC);
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// Keep track of the bits in the register we already emitted, so we
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// can avoid emitting redundant aliasing subregs. Because this is
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// just doing a greedy scan of all subregisters, it is possible that
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// this doesn't find a combination of subregisters that fully cover
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// the register (even though one may exist).
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SmallBitVector Coverage(RegSize, false);
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for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
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unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
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unsigned Size = TRI.getSubRegIdxSize(Idx);
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unsigned Offset = TRI.getSubRegIdxOffset(Idx);
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Reg = TRI.getDwarfRegNum(*SR, false);
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if (Reg < 0)
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continue;
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// Used to build the intersection between the bits we already
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// emitted and the bits covered by this subregister.
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SmallBitVector CurSubReg(RegSize, false);
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CurSubReg.set(Offset, Offset + Size);
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// If this sub-register has a DWARF number and we haven't covered
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// its range, and its range covers the value, emit a DWARF piece for it.
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if (Offset < MaxSize && CurSubReg.test(Coverage)) {
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// Emit a piece for any gap in the coverage.
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if (Offset > CurPos)
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DwarfRegs.push_back(Register::createSubRegister(
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-1, Offset - CurPos, "no DWARF register encoding"));
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if (Offset == 0 && Size >= MaxSize)
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DwarfRegs.push_back(Register::createRegister(Reg, "sub-register"));
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else
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DwarfRegs.push_back(Register::createSubRegister(
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Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"));
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}
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// Mark it as emitted.
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Coverage.set(Offset, Offset + Size);
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CurPos = Offset + Size;
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}
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// Failed to find any DWARF encoding.
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if (CurPos == 0)
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return false;
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// Found a partial or complete DWARF encoding.
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if (CurPos < RegSize)
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DwarfRegs.push_back(Register::createSubRegister(
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-1, RegSize - CurPos, "no DWARF register encoding"));
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return true;
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}
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void DwarfExpression::addStackValue() {
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if (DwarfVersion >= 4)
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emitOp(dwarf::DW_OP_stack_value);
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}
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void DwarfExpression::addSignedConstant(int64_t Value) {
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assert(isImplicitLocation() || isUnknownLocation());
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LocationKind = Implicit;
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emitOp(dwarf::DW_OP_consts);
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emitSigned(Value);
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}
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void DwarfExpression::addUnsignedConstant(uint64_t Value) {
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assert(isImplicitLocation() || isUnknownLocation());
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LocationKind = Implicit;
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emitConstu(Value);
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}
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void DwarfExpression::addUnsignedConstant(const APInt &Value) {
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assert(isImplicitLocation() || isUnknownLocation());
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LocationKind = Implicit;
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unsigned Size = Value.getBitWidth();
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const uint64_t *Data = Value.getRawData();
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// Chop it up into 64-bit pieces, because that's the maximum that
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// addUnsignedConstant takes.
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unsigned Offset = 0;
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while (Offset < Size) {
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addUnsignedConstant(*Data++);
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if (Offset == 0 && Size <= 64)
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break;
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addStackValue();
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addOpPiece(std::min(Size - Offset, 64u), Offset);
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Offset += 64;
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}
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}
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void DwarfExpression::addConstantFP(const APFloat &APF, const AsmPrinter &AP) {
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assert(isImplicitLocation() || isUnknownLocation());
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APInt API = APF.bitcastToAPInt();
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int NumBytes = API.getBitWidth() / 8;
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if (NumBytes == 4 /*float*/ || NumBytes == 8 /*double*/) {
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// FIXME: Add support for `long double`.
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emitOp(dwarf::DW_OP_implicit_value);
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emitUnsigned(NumBytes /*Size of the block in bytes*/);
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// The loop below is emitting the value starting at least significant byte,
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// so we need to perform a byte-swap to get the byte order correct in case
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// of a big-endian target.
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if (AP.getDataLayout().isBigEndian())
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API = API.byteSwap();
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for (int i = 0; i < NumBytes; ++i) {
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emitData1(API.getZExtValue() & 0xFF);
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API = API.lshr(8);
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}
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return;
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}
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LLVM_DEBUG(
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dbgs() << "Skipped DW_OP_implicit_value creation for ConstantFP of size: "
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<< API.getBitWidth() << " bits\n");
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}
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bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
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DIExpressionCursor &ExprCursor,
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llvm::Register MachineReg,
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unsigned FragmentOffsetInBits) {
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auto Fragment = ExprCursor.getFragmentInfo();
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if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
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LocationKind = Unknown;
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return false;
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}
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bool HasComplexExpression = false;
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auto Op = ExprCursor.peek();
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if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
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HasComplexExpression = true;
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// If the register can only be described by a complex expression (i.e.,
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// multiple subregisters) it doesn't safely compose with another complex
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// expression. For example, it is not possible to apply a DW_OP_deref
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// operation to multiple DW_OP_pieces, since composite location descriptions
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// do not push anything on the DWARF stack.
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//
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// DW_OP_entry_value operations can only hold a DWARF expression or a
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// register location description, so we can't emit a single entry value
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// covering a composite location description. In the future we may want to
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// emit entry value operations for each register location in the composite
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// location, but until that is supported do not emit anything.
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if ((HasComplexExpression || IsEmittingEntryValue) && DwarfRegs.size() > 1) {
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if (IsEmittingEntryValue)
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cancelEntryValue();
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DwarfRegs.clear();
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LocationKind = Unknown;
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return false;
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}
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// Handle simple register locations. If we are supposed to emit
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// a call site parameter expression and if that expression is just a register
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// location, emit it with addBReg and offset 0, because we should emit a DWARF
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// expression representing a value, rather than a location.
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if (!isMemoryLocation() && !HasComplexExpression &&
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(!isParameterValue() || isEntryValue())) {
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for (auto &Reg : DwarfRegs) {
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if (Reg.DwarfRegNo >= 0)
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addReg(Reg.DwarfRegNo, Reg.Comment);
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addOpPiece(Reg.SubRegSize);
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}
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if (isEntryValue())
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finalizeEntryValue();
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if (isEntryValue() && !isIndirect() && !isParameterValue() &&
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DwarfVersion >= 4)
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emitOp(dwarf::DW_OP_stack_value);
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DwarfRegs.clear();
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return true;
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}
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// Don't emit locations that cannot be expressed without DW_OP_stack_value.
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if (DwarfVersion < 4)
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if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
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return Op.getOp() == dwarf::DW_OP_stack_value;
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})) {
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DwarfRegs.clear();
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LocationKind = Unknown;
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return false;
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}
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assert(DwarfRegs.size() == 1);
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auto Reg = DwarfRegs[0];
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bool FBReg = isFrameRegister(TRI, MachineReg);
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int SignedOffset = 0;
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assert(!Reg.isSubRegister() && "full register expected");
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// Pattern-match combinations for which more efficient representations exist.
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// [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
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if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
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uint64_t Offset = Op->getArg(0);
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uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
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if (Offset <= IntMax) {
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SignedOffset = Offset;
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ExprCursor.take();
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}
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}
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// [Reg, DW_OP_constu, Offset, DW_OP_plus] --> [DW_OP_breg, Offset]
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// [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
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// If Reg is a subregister we need to mask it out before subtracting.
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if (Op && Op->getOp() == dwarf::DW_OP_constu) {
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uint64_t Offset = Op->getArg(0);
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uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
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auto N = ExprCursor.peekNext();
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if (N && N->getOp() == dwarf::DW_OP_plus && Offset <= IntMax) {
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SignedOffset = Offset;
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ExprCursor.consume(2);
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} else if (N && N->getOp() == dwarf::DW_OP_minus &&
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!SubRegisterSizeInBits && Offset <= IntMax + 1) {
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SignedOffset = -static_cast<int64_t>(Offset);
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ExprCursor.consume(2);
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}
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}
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if (FBReg)
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addFBReg(SignedOffset);
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else
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addBReg(Reg.DwarfRegNo, SignedOffset);
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DwarfRegs.clear();
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return true;
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}
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void DwarfExpression::setEntryValueFlags(const MachineLocation &Loc) {
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LocationFlags |= EntryValue;
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if (Loc.isIndirect())
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LocationFlags |= Indirect;
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}
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void DwarfExpression::setLocation(const MachineLocation &Loc,
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const DIExpression *DIExpr) {
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if (Loc.isIndirect())
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// Do not treat entry value descriptions of indirect parameters as memory
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// locations. This allows DwarfExpression::addReg() to add DW_OP_regN to an
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// entry value description.
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if (!DIExpr->isEntryValue())
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setMemoryLocationKind();
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if (DIExpr->isEntryValue())
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setEntryValueFlags(Loc);
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}
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void DwarfExpression::beginEntryValueExpression(
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DIExpressionCursor &ExprCursor) {
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auto Op = ExprCursor.take();
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(void)Op;
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assert(Op && Op->getOp() == dwarf::DW_OP_LLVM_entry_value);
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assert(!isMemoryLocation() &&
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"We don't support entry values of memory locations yet");
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assert(!IsEmittingEntryValue && "Already emitting entry value?");
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assert(Op->getArg(0) == 1 &&
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"Can currently only emit entry values covering a single operation");
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IsEmittingEntryValue = true;
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enableTemporaryBuffer();
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}
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void DwarfExpression::finalizeEntryValue() {
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assert(IsEmittingEntryValue && "Entry value not open?");
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disableTemporaryBuffer();
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emitOp(CU.getDwarf5OrGNULocationAtom(dwarf::DW_OP_entry_value));
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// Emit the entry value's size operand.
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unsigned Size = getTemporaryBufferSize();
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emitUnsigned(Size);
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// Emit the entry value's DWARF block operand.
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commitTemporaryBuffer();
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IsEmittingEntryValue = false;
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}
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void DwarfExpression::cancelEntryValue() {
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assert(IsEmittingEntryValue && "Entry value not open?");
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disableTemporaryBuffer();
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// The temporary buffer can't be emptied, so for now just assert that nothing
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// has been emitted to it.
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assert(getTemporaryBufferSize() == 0 &&
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"Began emitting entry value block before cancelling entry value");
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IsEmittingEntryValue = false;
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}
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unsigned DwarfExpression::getOrCreateBaseType(unsigned BitSize,
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dwarf::TypeKind Encoding) {
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// Reuse the base_type if we already have one in this CU otherwise we
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// create a new one.
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unsigned I = 0, E = CU.ExprRefedBaseTypes.size();
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for (; I != E; ++I)
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if (CU.ExprRefedBaseTypes[I].BitSize == BitSize &&
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CU.ExprRefedBaseTypes[I].Encoding == Encoding)
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break;
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if (I == E)
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CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding);
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return I;
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}
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/// Assuming a well-formed expression, match "DW_OP_deref*
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/// DW_OP_LLVM_fragment?".
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static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
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while (ExprCursor) {
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auto Op = ExprCursor.take();
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switch (Op->getOp()) {
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case dwarf::DW_OP_deref:
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case dwarf::DW_OP_LLVM_fragment:
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break;
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default:
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return false;
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}
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}
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return true;
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}
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void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
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unsigned FragmentOffsetInBits) {
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// Entry values can currently only cover the initial register location,
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// and not any other parts of the following DWARF expression.
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assert(!IsEmittingEntryValue && "Can't emit entry value around expression");
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// If we need to mask out a subregister, do it now, unless the next
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// operation would emit an OpPiece anyway.
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auto N = ExprCursor.peek();
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if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
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maskSubRegister();
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Optional<DIExpression::ExprOperand> PrevConvertOp = None;
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while (ExprCursor) {
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auto Op = ExprCursor.take();
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uint64_t OpNum = Op->getOp();
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if (OpNum >= dwarf::DW_OP_reg0 && OpNum <= dwarf::DW_OP_reg31) {
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emitOp(OpNum);
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continue;
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} else if (OpNum >= dwarf::DW_OP_breg0 && OpNum <= dwarf::DW_OP_breg31) {
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addBReg(OpNum - dwarf::DW_OP_breg0, Op->getArg(0));
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continue;
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}
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switch (OpNum) {
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case dwarf::DW_OP_LLVM_fragment: {
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unsigned SizeInBits = Op->getArg(1);
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unsigned FragmentOffset = Op->getArg(0);
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// The fragment offset must have already been adjusted by emitting an
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// empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
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// location.
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assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
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|
assert(SizeInBits >= OffsetInBits - FragmentOffset && "size underflow");
|
|
|
|
// If addMachineReg already emitted DW_OP_piece operations to represent
|
|
// a super-register by splicing together sub-registers, subtract the size
|
|
// of the pieces that was already emitted.
|
|
SizeInBits -= OffsetInBits - FragmentOffset;
|
|
|
|
// If addMachineReg requested a DW_OP_bit_piece to stencil out a
|
|
// sub-register that is smaller than the current fragment's size, use it.
|
|
if (SubRegisterSizeInBits)
|
|
SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
|
|
|
|
// Emit a DW_OP_stack_value for implicit location descriptions.
|
|
if (isImplicitLocation())
|
|
addStackValue();
|
|
|
|
// Emit the DW_OP_piece.
|
|
addOpPiece(SizeInBits, SubRegisterOffsetInBits);
|
|
setSubRegisterPiece(0, 0);
|
|
// Reset the location description kind.
|
|
LocationKind = Unknown;
|
|
return;
|
|
}
|
|
case dwarf::DW_OP_plus_uconst:
|
|
assert(!isRegisterLocation());
|
|
emitOp(dwarf::DW_OP_plus_uconst);
|
|
emitUnsigned(Op->getArg(0));
|
|
break;
|
|
case dwarf::DW_OP_plus:
|
|
case dwarf::DW_OP_minus:
|
|
case dwarf::DW_OP_mul:
|
|
case dwarf::DW_OP_div:
|
|
case dwarf::DW_OP_mod:
|
|
case dwarf::DW_OP_or:
|
|
case dwarf::DW_OP_and:
|
|
case dwarf::DW_OP_xor:
|
|
case dwarf::DW_OP_shl:
|
|
case dwarf::DW_OP_shr:
|
|
case dwarf::DW_OP_shra:
|
|
case dwarf::DW_OP_lit0:
|
|
case dwarf::DW_OP_not:
|
|
case dwarf::DW_OP_dup:
|
|
case dwarf::DW_OP_push_object_address:
|
|
case dwarf::DW_OP_over:
|
|
emitOp(OpNum);
|
|
break;
|
|
case dwarf::DW_OP_deref:
|
|
assert(!isRegisterLocation());
|
|
if (!isMemoryLocation() && ::isMemoryLocation(ExprCursor))
|
|
// Turning this into a memory location description makes the deref
|
|
// implicit.
|
|
LocationKind = Memory;
|
|
else
|
|
emitOp(dwarf::DW_OP_deref);
|
|
break;
|
|
case dwarf::DW_OP_constu:
|
|
assert(!isRegisterLocation());
|
|
emitConstu(Op->getArg(0));
|
|
break;
|
|
case dwarf::DW_OP_consts:
|
|
assert(!isRegisterLocation());
|
|
emitOp(dwarf::DW_OP_consts);
|
|
emitSigned(Op->getArg(0));
|
|
break;
|
|
case dwarf::DW_OP_LLVM_convert: {
|
|
unsigned BitSize = Op->getArg(0);
|
|
dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1));
|
|
if (DwarfVersion >= 5 && CU.getDwarfDebug().useOpConvert()) {
|
|
emitOp(dwarf::DW_OP_convert);
|
|
// If targeting a location-list; simply emit the index into the raw
|
|
// byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been
|
|
// fitted with means to extract it later.
|
|
// If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef
|
|
// (containing the index and a resolve mechanism during emit) into the
|
|
// DIE value list.
|
|
emitBaseTypeRef(getOrCreateBaseType(BitSize, Encoding));
|
|
} else {
|
|
if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) {
|
|
if (Encoding == dwarf::DW_ATE_signed)
|
|
emitLegacySExt(PrevConvertOp->getArg(0));
|
|
else if (Encoding == dwarf::DW_ATE_unsigned)
|
|
emitLegacyZExt(PrevConvertOp->getArg(0));
|
|
PrevConvertOp = None;
|
|
} else {
|
|
PrevConvertOp = Op;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case dwarf::DW_OP_stack_value:
|
|
LocationKind = Implicit;
|
|
break;
|
|
case dwarf::DW_OP_swap:
|
|
assert(!isRegisterLocation());
|
|
emitOp(dwarf::DW_OP_swap);
|
|
break;
|
|
case dwarf::DW_OP_xderef:
|
|
assert(!isRegisterLocation());
|
|
emitOp(dwarf::DW_OP_xderef);
|
|
break;
|
|
case dwarf::DW_OP_deref_size:
|
|
emitOp(dwarf::DW_OP_deref_size);
|
|
emitData1(Op->getArg(0));
|
|
break;
|
|
case dwarf::DW_OP_LLVM_tag_offset:
|
|
TagOffset = Op->getArg(0);
|
|
break;
|
|
case dwarf::DW_OP_regx:
|
|
emitOp(dwarf::DW_OP_regx);
|
|
emitUnsigned(Op->getArg(0));
|
|
break;
|
|
case dwarf::DW_OP_bregx:
|
|
emitOp(dwarf::DW_OP_bregx);
|
|
emitUnsigned(Op->getArg(0));
|
|
emitSigned(Op->getArg(1));
|
|
break;
|
|
default:
|
|
llvm_unreachable("unhandled opcode found in expression");
|
|
}
|
|
}
|
|
|
|
if (isImplicitLocation() && !isParameterValue())
|
|
// Turn this into an implicit location description.
|
|
addStackValue();
|
|
}
|
|
|
|
/// add masking operations to stencil out a subregister.
|
|
void DwarfExpression::maskSubRegister() {
|
|
assert(SubRegisterSizeInBits && "no subregister was registered");
|
|
if (SubRegisterOffsetInBits > 0)
|
|
addShr(SubRegisterOffsetInBits);
|
|
uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
|
|
addAnd(Mask);
|
|
}
|
|
|
|
void DwarfExpression::finalize() {
|
|
assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
|
|
// Emit any outstanding DW_OP_piece operations to mask out subregisters.
|
|
if (SubRegisterSizeInBits == 0)
|
|
return;
|
|
// Don't emit a DW_OP_piece for a subregister at offset 0.
|
|
if (SubRegisterOffsetInBits == 0)
|
|
return;
|
|
addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
|
|
}
|
|
|
|
void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
|
|
if (!Expr || !Expr->isFragment())
|
|
return;
|
|
|
|
uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
|
|
assert(FragmentOffset >= OffsetInBits &&
|
|
"overlapping or duplicate fragments");
|
|
if (FragmentOffset > OffsetInBits)
|
|
addOpPiece(FragmentOffset - OffsetInBits);
|
|
OffsetInBits = FragmentOffset;
|
|
}
|
|
|
|
void DwarfExpression::emitLegacySExt(unsigned FromBits) {
|
|
// (((X >> (FromBits - 1)) * (~0)) << FromBits) | X
|
|
emitOp(dwarf::DW_OP_dup);
|
|
emitOp(dwarf::DW_OP_constu);
|
|
emitUnsigned(FromBits - 1);
|
|
emitOp(dwarf::DW_OP_shr);
|
|
emitOp(dwarf::DW_OP_lit0);
|
|
emitOp(dwarf::DW_OP_not);
|
|
emitOp(dwarf::DW_OP_mul);
|
|
emitOp(dwarf::DW_OP_constu);
|
|
emitUnsigned(FromBits);
|
|
emitOp(dwarf::DW_OP_shl);
|
|
emitOp(dwarf::DW_OP_or);
|
|
}
|
|
|
|
void DwarfExpression::emitLegacyZExt(unsigned FromBits) {
|
|
// (X & (1 << FromBits - 1))
|
|
emitOp(dwarf::DW_OP_constu);
|
|
emitUnsigned((1ULL << FromBits) - 1);
|
|
emitOp(dwarf::DW_OP_and);
|
|
}
|
|
|
|
void DwarfExpression::addWasmLocation(unsigned Index, uint64_t Offset) {
|
|
assert(LocationKind == Implicit || LocationKind == Unknown);
|
|
LocationKind = Implicit;
|
|
emitOp(dwarf::DW_OP_WASM_location);
|
|
emitUnsigned(Index);
|
|
emitUnsigned(Offset);
|
|
}
|