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377 lines
13 KiB
377 lines
13 KiB
//===-- RuntimeDyldCOFFAArch64.h --- COFF/AArch64 specific code ---*- C++
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//-*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// COFF AArch64 support for MC-JIT runtime dynamic linker.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_EXECUTIONENGINE_RUNTIMEDYLD_TARGETS_RUNTIMEDYLDCOFFAARCH64_H
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#define LLVM_LIB_EXECUTIONENGINE_RUNTIMEDYLD_TARGETS_RUNTIMEDYLDCOFFAARCH64_H
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#include "../RuntimeDyldCOFF.h"
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#include "llvm/BinaryFormat/COFF.h"
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#include "llvm/Object/COFF.h"
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#include "llvm/Support/Endian.h"
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#define DEBUG_TYPE "dyld"
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using namespace llvm::support::endian;
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namespace llvm {
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// This relocation type is used for handling long branch instruction
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// throught the Stub.
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enum InternalRelocationType : unsigned {
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INTERNAL_REL_ARM64_LONG_BRANCH26 = 0x111,
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};
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static void add16(uint8_t *p, int16_t v) { write16le(p, read16le(p) + v); }
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static void or32le(void *P, int32_t V) { write32le(P, read32le(P) | V); }
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static void write32AArch64Imm(uint8_t *T, uint64_t imm, uint32_t rangeLimit) {
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uint32_t orig = read32le(T);
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orig &= ~(0xFFF << 10);
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write32le(T, orig | ((imm & (0xFFF >> rangeLimit)) << 10));
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}
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static void write32AArch64Ldr(uint8_t *T, uint64_t imm) {
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uint32_t orig = read32le(T);
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uint32_t size = orig >> 30;
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// 0x04000000 indicates SIMD/FP registers
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// 0x00800000 indicates 128 bit
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if ((orig & 0x04800000) == 0x04800000)
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size += 4;
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if ((imm & ((1 << size) - 1)) != 0)
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assert(0 && "misaligned ldr/str offset");
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write32AArch64Imm(T, imm >> size, size);
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}
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static void write32AArch64Addr(void *T, uint64_t s, uint64_t p, int shift) {
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uint64_t Imm = (s >> shift) - (p >> shift);
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uint32_t ImmLo = (Imm & 0x3) << 29;
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uint32_t ImmHi = (Imm & 0x1FFFFC) << 3;
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uint64_t Mask = (0x3 << 29) | (0x1FFFFC << 3);
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write32le(T, (read32le(T) & ~Mask) | ImmLo | ImmHi);
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}
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class RuntimeDyldCOFFAArch64 : public RuntimeDyldCOFF {
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private:
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// When a module is loaded we save the SectionID of the unwind
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// sections in a table until we receive a request to register all
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// unregisteredEH frame sections with the memory manager.
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SmallVector<SID, 2> UnregisteredEHFrameSections;
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SmallVector<SID, 2> RegisteredEHFrameSections;
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uint64_t ImageBase;
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// Fake an __ImageBase pointer by returning the section with the lowest adress
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uint64_t getImageBase() {
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if (!ImageBase) {
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ImageBase = std::numeric_limits<uint64_t>::max();
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for (const SectionEntry &Section : Sections)
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// The Sections list may contain sections that weren't loaded for
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// whatever reason: they may be debug sections, and ProcessAllSections
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// is false, or they may be sections that contain 0 bytes. If the
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// section isn't loaded, the load address will be 0, and it should not
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// be included in the ImageBase calculation.
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if (Section.getLoadAddress() != 0)
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ImageBase = std::min(ImageBase, Section.getLoadAddress());
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}
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return ImageBase;
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}
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public:
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RuntimeDyldCOFFAArch64(RuntimeDyld::MemoryManager &MM,
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JITSymbolResolver &Resolver)
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: RuntimeDyldCOFF(MM, Resolver, 8, COFF::IMAGE_REL_ARM64_ADDR64),
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ImageBase(0) {}
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unsigned getStubAlignment() override { return 8; }
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unsigned getMaxStubSize() const override { return 20; }
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std::tuple<uint64_t, uint64_t, uint64_t>
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generateRelocationStub(unsigned SectionID, StringRef TargetName,
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uint64_t Offset, uint64_t RelType, uint64_t Addend,
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StubMap &Stubs) {
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uintptr_t StubOffset;
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SectionEntry &Section = Sections[SectionID];
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RelocationValueRef OriginalRelValueRef;
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OriginalRelValueRef.SectionID = SectionID;
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OriginalRelValueRef.Offset = Offset;
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OriginalRelValueRef.Addend = Addend;
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OriginalRelValueRef.SymbolName = TargetName.data();
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auto Stub = Stubs.find(OriginalRelValueRef);
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if (Stub == Stubs.end()) {
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LLVM_DEBUG(dbgs() << " Create a new stub function for "
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<< TargetName.data() << "\n");
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StubOffset = Section.getStubOffset();
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Stubs[OriginalRelValueRef] = StubOffset;
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createStubFunction(Section.getAddressWithOffset(StubOffset));
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Section.advanceStubOffset(getMaxStubSize());
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} else {
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LLVM_DEBUG(dbgs() << " Stub function found for " << TargetName.data()
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<< "\n");
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StubOffset = Stub->second;
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}
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// Resolve original relocation to stub function.
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const RelocationEntry RE(SectionID, Offset, RelType, Addend);
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resolveRelocation(RE, Section.getLoadAddressWithOffset(StubOffset));
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// adjust relocation info so resolution writes to the stub function
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// Here an internal relocation type is used for resolving long branch via
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// stub instruction.
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Addend = 0;
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Offset = StubOffset;
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RelType = INTERNAL_REL_ARM64_LONG_BRANCH26;
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return std::make_tuple(Offset, RelType, Addend);
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}
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Expected<object::relocation_iterator>
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processRelocationRef(unsigned SectionID, object::relocation_iterator RelI,
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const object::ObjectFile &Obj,
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ObjSectionToIDMap &ObjSectionToID,
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StubMap &Stubs) override {
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auto Symbol = RelI->getSymbol();
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if (Symbol == Obj.symbol_end())
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report_fatal_error("Unknown symbol in relocation");
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Expected<StringRef> TargetNameOrErr = Symbol->getName();
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if (!TargetNameOrErr)
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return TargetNameOrErr.takeError();
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StringRef TargetName = *TargetNameOrErr;
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auto SectionOrErr = Symbol->getSection();
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if (!SectionOrErr)
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return SectionOrErr.takeError();
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auto Section = *SectionOrErr;
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uint64_t RelType = RelI->getType();
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uint64_t Offset = RelI->getOffset();
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// If there is no section, this must be an external reference.
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bool IsExtern = Section == Obj.section_end();
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// Determine the Addend used to adjust the relocation value.
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uint64_t Addend = 0;
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SectionEntry &AddendSection = Sections[SectionID];
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uintptr_t ObjTarget = AddendSection.getObjAddress() + Offset;
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uint8_t *Displacement = (uint8_t *)ObjTarget;
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unsigned TargetSectionID = -1;
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uint64_t TargetOffset = -1;
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if (TargetName.startswith(getImportSymbolPrefix())) {
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TargetSectionID = SectionID;
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TargetOffset = getDLLImportOffset(SectionID, Stubs, TargetName);
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TargetName = StringRef();
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IsExtern = false;
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} else if (!IsExtern) {
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if (auto TargetSectionIDOrErr = findOrEmitSection(
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Obj, *Section, Section->isText(), ObjSectionToID))
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TargetSectionID = *TargetSectionIDOrErr;
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else
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return TargetSectionIDOrErr.takeError();
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TargetOffset = getSymbolOffset(*Symbol);
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}
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switch (RelType) {
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case COFF::IMAGE_REL_ARM64_ADDR32:
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case COFF::IMAGE_REL_ARM64_ADDR32NB:
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case COFF::IMAGE_REL_ARM64_REL32:
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case COFF::IMAGE_REL_ARM64_SECREL:
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Addend = read32le(Displacement);
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break;
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case COFF::IMAGE_REL_ARM64_BRANCH26: {
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uint32_t orig = read32le(Displacement);
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Addend = (orig & 0x03FFFFFF) << 2;
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if (IsExtern)
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std::tie(Offset, RelType, Addend) = generateRelocationStub(
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SectionID, TargetName, Offset, RelType, Addend, Stubs);
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break;
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}
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case COFF::IMAGE_REL_ARM64_BRANCH19: {
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uint32_t orig = read32le(Displacement);
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Addend = (orig & 0x00FFFFE0) >> 3;
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break;
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}
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case COFF::IMAGE_REL_ARM64_BRANCH14: {
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uint32_t orig = read32le(Displacement);
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Addend = (orig & 0x000FFFE0) >> 3;
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break;
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}
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case COFF::IMAGE_REL_ARM64_REL21:
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case COFF::IMAGE_REL_ARM64_PAGEBASE_REL21: {
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uint32_t orig = read32le(Displacement);
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Addend = ((orig >> 29) & 0x3) | ((orig >> 3) & 0x1FFFFC);
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break;
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}
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case COFF::IMAGE_REL_ARM64_PAGEOFFSET_12L:
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case COFF::IMAGE_REL_ARM64_PAGEOFFSET_12A: {
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uint32_t orig = read32le(Displacement);
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Addend = ((orig >> 10) & 0xFFF);
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break;
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}
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case COFF::IMAGE_REL_ARM64_ADDR64: {
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Addend = read64le(Displacement);
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break;
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}
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default:
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break;
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}
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#if !defined(NDEBUG)
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SmallString<32> RelTypeName;
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RelI->getTypeName(RelTypeName);
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LLVM_DEBUG(dbgs() << "\t\tIn Section " << SectionID << " Offset " << Offset
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<< " RelType: " << RelTypeName << " TargetName: "
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<< TargetName << " Addend " << Addend << "\n");
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#endif
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if (IsExtern) {
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RelocationEntry RE(SectionID, Offset, RelType, Addend);
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addRelocationForSymbol(RE, TargetName);
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} else {
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RelocationEntry RE(SectionID, Offset, RelType, TargetOffset + Addend);
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addRelocationForSection(RE, TargetSectionID);
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}
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return ++RelI;
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}
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void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override {
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const auto Section = Sections[RE.SectionID];
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uint8_t *Target = Section.getAddressWithOffset(RE.Offset);
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uint64_t FinalAddress = Section.getLoadAddressWithOffset(RE.Offset);
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switch (RE.RelType) {
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default:
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llvm_unreachable("unsupported relocation type");
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case COFF::IMAGE_REL_ARM64_ABSOLUTE: {
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// This relocation is ignored.
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break;
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}
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case COFF::IMAGE_REL_ARM64_PAGEBASE_REL21: {
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// The page base of the target, for ADRP instruction.
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Value += RE.Addend;
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write32AArch64Addr(Target, Value, FinalAddress, 12);
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break;
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}
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case COFF::IMAGE_REL_ARM64_REL21: {
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// The 12-bit relative displacement to the target, for instruction ADR
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Value += RE.Addend;
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write32AArch64Addr(Target, Value, FinalAddress, 0);
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break;
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}
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case COFF::IMAGE_REL_ARM64_PAGEOFFSET_12A: {
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// The 12-bit page offset of the target,
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// for instructions ADD/ADDS (immediate) with zero shift.
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Value += RE.Addend;
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write32AArch64Imm(Target, Value & 0xFFF, 0);
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break;
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}
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case COFF::IMAGE_REL_ARM64_PAGEOFFSET_12L: {
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// The 12-bit page offset of the target,
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// for instruction LDR (indexed, unsigned immediate).
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Value += RE.Addend;
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write32AArch64Ldr(Target, Value & 0xFFF);
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break;
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}
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case COFF::IMAGE_REL_ARM64_ADDR32: {
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// The 32-bit VA of the target.
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uint32_t VA = Value + RE.Addend;
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write32le(Target, VA);
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break;
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}
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case COFF::IMAGE_REL_ARM64_ADDR32NB: {
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// The target's 32-bit RVA.
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uint64_t RVA = Value + RE.Addend - getImageBase();
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write32le(Target, RVA);
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break;
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}
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case INTERNAL_REL_ARM64_LONG_BRANCH26: {
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// Encode the immadiate value for generated Stub instruction (MOVZ)
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or32le(Target + 12, ((Value + RE.Addend) & 0xFFFF) << 5);
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or32le(Target + 8, ((Value + RE.Addend) & 0xFFFF0000) >> 11);
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or32le(Target + 4, ((Value + RE.Addend) & 0xFFFF00000000) >> 27);
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or32le(Target + 0, ((Value + RE.Addend) & 0xFFFF000000000000) >> 43);
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break;
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}
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case COFF::IMAGE_REL_ARM64_BRANCH26: {
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// The 26-bit relative displacement to the target, for B and BL
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// instructions.
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uint64_t PCRelVal = Value + RE.Addend - FinalAddress;
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assert(isInt<28>(PCRelVal) && "Branch target is out of range.");
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write32le(Target, (read32le(Target) & ~(0x03FFFFFF)) |
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(PCRelVal & 0x0FFFFFFC) >> 2);
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break;
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}
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case COFF::IMAGE_REL_ARM64_BRANCH19: {
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// The 19-bit offset to the relocation target,
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// for conditional B instruction.
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uint64_t PCRelVal = Value + RE.Addend - FinalAddress;
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assert(isInt<21>(PCRelVal) && "Branch target is out of range.");
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write32le(Target, (read32le(Target) & ~(0x00FFFFE0)) |
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(PCRelVal & 0x001FFFFC) << 3);
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break;
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}
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case COFF::IMAGE_REL_ARM64_BRANCH14: {
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// The 14-bit offset to the relocation target,
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// for instructions TBZ and TBNZ.
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uint64_t PCRelVal = Value + RE.Addend - FinalAddress;
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assert(isInt<16>(PCRelVal) && "Branch target is out of range.");
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write32le(Target, (read32le(Target) & ~(0x000FFFE0)) |
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(PCRelVal & 0x0000FFFC) << 3);
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break;
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}
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case COFF::IMAGE_REL_ARM64_ADDR64: {
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// The 64-bit VA of the relocation target.
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write64le(Target, Value + RE.Addend);
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break;
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}
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case COFF::IMAGE_REL_ARM64_SECTION: {
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// 16-bit section index of the section that contains the target.
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assert(static_cast<uint32_t>(RE.SectionID) <= UINT16_MAX &&
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"relocation overflow");
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add16(Target, RE.SectionID);
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break;
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}
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case COFF::IMAGE_REL_ARM64_SECREL: {
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// 32-bit offset of the target from the beginning of its section.
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assert(static_cast<int64_t>(RE.Addend) <= INT32_MAX &&
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"Relocation overflow");
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assert(static_cast<int64_t>(RE.Addend) >= INT32_MIN &&
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"Relocation underflow");
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write32le(Target, RE.Addend);
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break;
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}
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case COFF::IMAGE_REL_ARM64_REL32: {
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// The 32-bit relative address from the byte following the relocation.
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uint64_t Result = Value - FinalAddress - 4;
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write32le(Target, Result + RE.Addend);
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break;
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}
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}
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}
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void registerEHFrames() override {}
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};
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} // End namespace llvm
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#endif
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