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879 lines
28 KiB
879 lines
28 KiB
//===-- SILowerI1Copies.cpp - Lower I1 Copies -----------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass lowers all occurrences of i1 values (with a vreg_1 register class)
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// to lane masks (32 / 64-bit scalar registers). The pass assumes machine SSA
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// form and a wave-level control flow graph.
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//
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// Before this pass, values that are semantically i1 and are defined and used
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// within the same basic block are already represented as lane masks in scalar
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// registers. However, values that cross basic blocks are always transferred
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// between basic blocks in vreg_1 virtual registers and are lowered by this
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// pass.
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//
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// The only instructions that use or define vreg_1 virtual registers are COPY,
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// PHI, and IMPLICIT_DEF.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachinePostDominators.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineSSAUpdater.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetMachine.h"
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#define DEBUG_TYPE "si-i1-copies"
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using namespace llvm;
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static unsigned createLaneMaskReg(MachineFunction &MF);
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static unsigned insertUndefLaneMask(MachineBasicBlock &MBB);
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namespace {
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class SILowerI1Copies : public MachineFunctionPass {
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public:
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static char ID;
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private:
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bool IsWave32 = false;
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MachineFunction *MF = nullptr;
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MachineDominatorTree *DT = nullptr;
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MachinePostDominatorTree *PDT = nullptr;
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MachineRegisterInfo *MRI = nullptr;
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const GCNSubtarget *ST = nullptr;
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const SIInstrInfo *TII = nullptr;
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unsigned ExecReg;
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unsigned MovOp;
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unsigned AndOp;
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unsigned OrOp;
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unsigned XorOp;
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unsigned AndN2Op;
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unsigned OrN2Op;
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DenseSet<unsigned> ConstrainRegs;
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public:
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SILowerI1Copies() : MachineFunctionPass(ID) {
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initializeSILowerI1CopiesPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "SI Lower i1 Copies"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<MachinePostDominatorTree>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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void lowerCopiesFromI1();
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void lowerPhis();
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void lowerCopiesToI1();
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bool isConstantLaneMask(Register Reg, bool &Val) const;
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void buildMergeLaneMasks(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, const DebugLoc &DL,
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unsigned DstReg, unsigned PrevReg, unsigned CurReg);
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MachineBasicBlock::iterator
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getSaluInsertionAtEnd(MachineBasicBlock &MBB) const;
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bool isVreg1(Register Reg) const {
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return Reg.isVirtual() && MRI->getRegClass(Reg) == &AMDGPU::VReg_1RegClass;
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}
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bool isLaneMaskReg(unsigned Reg) const {
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return TII->getRegisterInfo().isSGPRReg(*MRI, Reg) &&
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TII->getRegisterInfo().getRegSizeInBits(Reg, *MRI) ==
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ST->getWavefrontSize();
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}
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};
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/// Helper class that determines the relationship between incoming values of a
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/// phi in the control flow graph to determine where an incoming value can
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/// simply be taken as a scalar lane mask as-is, and where it needs to be
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/// merged with another, previously defined lane mask.
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///
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/// The approach is as follows:
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/// - Determine all basic blocks which, starting from the incoming blocks,
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/// a wave may reach before entering the def block (the block containing the
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/// phi).
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/// - If an incoming block has no predecessors in this set, we can take the
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/// incoming value as a scalar lane mask as-is.
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/// -- A special case of this is when the def block has a self-loop.
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/// - Otherwise, the incoming value needs to be merged with a previously
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/// defined lane mask.
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/// - If there is a path into the set of reachable blocks that does _not_ go
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/// through an incoming block where we can take the scalar lane mask as-is,
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/// we need to invent an available value for the SSAUpdater. Choices are
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/// 0 and undef, with differing consequences for how to merge values etc.
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///
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/// TODO: We could use region analysis to quickly skip over SESE regions during
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/// the traversal.
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///
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class PhiIncomingAnalysis {
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MachinePostDominatorTree &PDT;
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// For each reachable basic block, whether it is a source in the induced
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// subgraph of the CFG.
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DenseMap<MachineBasicBlock *, bool> ReachableMap;
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SmallVector<MachineBasicBlock *, 4> ReachableOrdered;
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SmallVector<MachineBasicBlock *, 4> Stack;
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SmallVector<MachineBasicBlock *, 4> Predecessors;
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public:
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PhiIncomingAnalysis(MachinePostDominatorTree &PDT) : PDT(PDT) {}
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/// Returns whether \p MBB is a source in the induced subgraph of reachable
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/// blocks.
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bool isSource(MachineBasicBlock &MBB) const {
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return ReachableMap.find(&MBB)->second;
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}
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ArrayRef<MachineBasicBlock *> predecessors() const { return Predecessors; }
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void analyze(MachineBasicBlock &DefBlock,
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ArrayRef<MachineBasicBlock *> IncomingBlocks) {
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assert(Stack.empty());
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ReachableMap.clear();
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ReachableOrdered.clear();
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Predecessors.clear();
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// Insert the def block first, so that it acts as an end point for the
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// traversal.
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ReachableMap.try_emplace(&DefBlock, false);
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ReachableOrdered.push_back(&DefBlock);
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for (MachineBasicBlock *MBB : IncomingBlocks) {
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if (MBB == &DefBlock) {
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ReachableMap[&DefBlock] = true; // self-loop on DefBlock
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continue;
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}
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ReachableMap.try_emplace(MBB, false);
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ReachableOrdered.push_back(MBB);
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// If this block has a divergent terminator and the def block is its
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// post-dominator, the wave may first visit the other successors.
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bool Divergent = false;
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for (MachineInstr &MI : MBB->terminators()) {
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if (MI.getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO ||
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MI.getOpcode() == AMDGPU::SI_IF ||
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MI.getOpcode() == AMDGPU::SI_ELSE ||
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MI.getOpcode() == AMDGPU::SI_LOOP) {
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Divergent = true;
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break;
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}
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}
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if (Divergent && PDT.dominates(&DefBlock, MBB)) {
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for (MachineBasicBlock *Succ : MBB->successors())
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Stack.push_back(Succ);
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}
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}
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while (!Stack.empty()) {
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MachineBasicBlock *MBB = Stack.pop_back_val();
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if (!ReachableMap.try_emplace(MBB, false).second)
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continue;
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ReachableOrdered.push_back(MBB);
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for (MachineBasicBlock *Succ : MBB->successors())
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Stack.push_back(Succ);
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}
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for (MachineBasicBlock *MBB : ReachableOrdered) {
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bool HaveReachablePred = false;
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for (MachineBasicBlock *Pred : MBB->predecessors()) {
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if (ReachableMap.count(Pred)) {
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HaveReachablePred = true;
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} else {
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Stack.push_back(Pred);
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}
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}
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if (!HaveReachablePred)
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ReachableMap[MBB] = true;
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if (HaveReachablePred) {
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for (MachineBasicBlock *UnreachablePred : Stack) {
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if (!llvm::is_contained(Predecessors, UnreachablePred))
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Predecessors.push_back(UnreachablePred);
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}
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}
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Stack.clear();
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}
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}
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};
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/// Helper class that detects loops which require us to lower an i1 COPY into
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/// bitwise manipulation.
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///
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/// Unfortunately, we cannot use LoopInfo because LoopInfo does not distinguish
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/// between loops with the same header. Consider this example:
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///
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/// A-+-+
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/// | | |
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/// B-+ |
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/// | |
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/// C---+
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///
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/// A is the header of a loop containing A, B, and C as far as LoopInfo is
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/// concerned. However, an i1 COPY in B that is used in C must be lowered to
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/// bitwise operations to combine results from different loop iterations when
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/// B has a divergent branch (since by default we will compile this code such
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/// that threads in a wave are merged at the entry of C).
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///
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/// The following rule is implemented to determine whether bitwise operations
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/// are required: use the bitwise lowering for a def in block B if a backward
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/// edge to B is reachable without going through the nearest common
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/// post-dominator of B and all uses of the def.
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///
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/// TODO: This rule is conservative because it does not check whether the
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/// relevant branches are actually divergent.
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///
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/// The class is designed to cache the CFG traversal so that it can be re-used
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/// for multiple defs within the same basic block.
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///
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/// TODO: We could use region analysis to quickly skip over SESE regions during
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/// the traversal.
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///
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class LoopFinder {
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MachineDominatorTree &DT;
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MachinePostDominatorTree &PDT;
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// All visited / reachable block, tagged by level (level 0 is the def block,
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// level 1 are all blocks reachable including but not going through the def
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// block's IPDOM, etc.).
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DenseMap<MachineBasicBlock *, unsigned> Visited;
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// Nearest common dominator of all visited blocks by level (level 0 is the
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// def block). Used for seeding the SSAUpdater.
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SmallVector<MachineBasicBlock *, 4> CommonDominators;
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// Post-dominator of all visited blocks.
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MachineBasicBlock *VisitedPostDom = nullptr;
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// Level at which a loop was found: 0 is not possible; 1 = a backward edge is
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// reachable without going through the IPDOM of the def block (if the IPDOM
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// itself has an edge to the def block, the loop level is 2), etc.
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unsigned FoundLoopLevel = ~0u;
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MachineBasicBlock *DefBlock = nullptr;
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SmallVector<MachineBasicBlock *, 4> Stack;
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SmallVector<MachineBasicBlock *, 4> NextLevel;
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public:
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LoopFinder(MachineDominatorTree &DT, MachinePostDominatorTree &PDT)
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: DT(DT), PDT(PDT) {}
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void initialize(MachineBasicBlock &MBB) {
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Visited.clear();
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CommonDominators.clear();
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Stack.clear();
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NextLevel.clear();
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VisitedPostDom = nullptr;
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FoundLoopLevel = ~0u;
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DefBlock = &MBB;
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}
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/// Check whether a backward edge can be reached without going through the
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/// given \p PostDom of the def block.
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///
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/// Return the level of \p PostDom if a loop was found, or 0 otherwise.
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unsigned findLoop(MachineBasicBlock *PostDom) {
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MachineDomTreeNode *PDNode = PDT.getNode(DefBlock);
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if (!VisitedPostDom)
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advanceLevel();
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unsigned Level = 0;
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while (PDNode->getBlock() != PostDom) {
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if (PDNode->getBlock() == VisitedPostDom)
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advanceLevel();
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PDNode = PDNode->getIDom();
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Level++;
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if (FoundLoopLevel == Level)
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return Level;
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}
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return 0;
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}
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/// Add undef values dominating the loop and the optionally given additional
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/// blocks, so that the SSA updater doesn't have to search all the way to the
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/// function entry.
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void addLoopEntries(unsigned LoopLevel, MachineSSAUpdater &SSAUpdater,
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ArrayRef<MachineBasicBlock *> Blocks = {}) {
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assert(LoopLevel < CommonDominators.size());
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MachineBasicBlock *Dom = CommonDominators[LoopLevel];
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for (MachineBasicBlock *MBB : Blocks)
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Dom = DT.findNearestCommonDominator(Dom, MBB);
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if (!inLoopLevel(*Dom, LoopLevel, Blocks)) {
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SSAUpdater.AddAvailableValue(Dom, insertUndefLaneMask(*Dom));
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} else {
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// The dominator is part of the loop or the given blocks, so add the
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// undef value to unreachable predecessors instead.
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for (MachineBasicBlock *Pred : Dom->predecessors()) {
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if (!inLoopLevel(*Pred, LoopLevel, Blocks))
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SSAUpdater.AddAvailableValue(Pred, insertUndefLaneMask(*Pred));
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}
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}
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}
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private:
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bool inLoopLevel(MachineBasicBlock &MBB, unsigned LoopLevel,
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ArrayRef<MachineBasicBlock *> Blocks) const {
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auto DomIt = Visited.find(&MBB);
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if (DomIt != Visited.end() && DomIt->second <= LoopLevel)
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return true;
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if (llvm::is_contained(Blocks, &MBB))
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return true;
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return false;
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}
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void advanceLevel() {
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MachineBasicBlock *VisitedDom;
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if (!VisitedPostDom) {
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VisitedPostDom = DefBlock;
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VisitedDom = DefBlock;
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Stack.push_back(DefBlock);
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} else {
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VisitedPostDom = PDT.getNode(VisitedPostDom)->getIDom()->getBlock();
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VisitedDom = CommonDominators.back();
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for (unsigned i = 0; i < NextLevel.size();) {
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if (PDT.dominates(VisitedPostDom, NextLevel[i])) {
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Stack.push_back(NextLevel[i]);
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NextLevel[i] = NextLevel.back();
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NextLevel.pop_back();
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} else {
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i++;
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}
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}
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}
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unsigned Level = CommonDominators.size();
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while (!Stack.empty()) {
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MachineBasicBlock *MBB = Stack.pop_back_val();
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if (!PDT.dominates(VisitedPostDom, MBB))
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NextLevel.push_back(MBB);
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Visited[MBB] = Level;
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VisitedDom = DT.findNearestCommonDominator(VisitedDom, MBB);
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for (MachineBasicBlock *Succ : MBB->successors()) {
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if (Succ == DefBlock) {
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if (MBB == VisitedPostDom)
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FoundLoopLevel = std::min(FoundLoopLevel, Level + 1);
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else
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FoundLoopLevel = std::min(FoundLoopLevel, Level);
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continue;
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}
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if (Visited.try_emplace(Succ, ~0u).second) {
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if (MBB == VisitedPostDom)
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NextLevel.push_back(Succ);
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else
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Stack.push_back(Succ);
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}
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}
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}
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CommonDominators.push_back(VisitedDom);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(SILowerI1Copies, DEBUG_TYPE, "SI Lower i1 Copies", false,
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false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree)
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INITIALIZE_PASS_END(SILowerI1Copies, DEBUG_TYPE, "SI Lower i1 Copies", false,
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false)
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char SILowerI1Copies::ID = 0;
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char &llvm::SILowerI1CopiesID = SILowerI1Copies::ID;
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FunctionPass *llvm::createSILowerI1CopiesPass() {
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return new SILowerI1Copies();
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}
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static unsigned createLaneMaskReg(MachineFunction &MF) {
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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return MRI.createVirtualRegister(ST.isWave32() ? &AMDGPU::SReg_32RegClass
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: &AMDGPU::SReg_64RegClass);
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}
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static unsigned insertUndefLaneMask(MachineBasicBlock &MBB) {
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MachineFunction &MF = *MBB.getParent();
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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const SIInstrInfo *TII = ST.getInstrInfo();
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unsigned UndefReg = createLaneMaskReg(MF);
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BuildMI(MBB, MBB.getFirstTerminator(), {}, TII->get(AMDGPU::IMPLICIT_DEF),
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UndefReg);
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return UndefReg;
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}
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/// Lower all instructions that def or use vreg_1 registers.
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///
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/// In a first pass, we lower COPYs from vreg_1 to vector registers, as can
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/// occur around inline assembly. We do this first, before vreg_1 registers
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/// are changed to scalar mask registers.
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///
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/// Then we lower all defs of vreg_1 registers. Phi nodes are lowered before
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/// all others, because phi lowering looks through copies and can therefore
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/// often make copy lowering unnecessary.
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bool SILowerI1Copies::runOnMachineFunction(MachineFunction &TheMF) {
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// Only need to run this in SelectionDAG path.
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if (TheMF.getProperties().hasProperty(
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MachineFunctionProperties::Property::Selected))
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return false;
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MF = &TheMF;
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MRI = &MF->getRegInfo();
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DT = &getAnalysis<MachineDominatorTree>();
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PDT = &getAnalysis<MachinePostDominatorTree>();
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ST = &MF->getSubtarget<GCNSubtarget>();
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TII = ST->getInstrInfo();
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IsWave32 = ST->isWave32();
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if (IsWave32) {
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ExecReg = AMDGPU::EXEC_LO;
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MovOp = AMDGPU::S_MOV_B32;
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AndOp = AMDGPU::S_AND_B32;
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OrOp = AMDGPU::S_OR_B32;
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XorOp = AMDGPU::S_XOR_B32;
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AndN2Op = AMDGPU::S_ANDN2_B32;
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OrN2Op = AMDGPU::S_ORN2_B32;
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} else {
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ExecReg = AMDGPU::EXEC;
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MovOp = AMDGPU::S_MOV_B64;
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AndOp = AMDGPU::S_AND_B64;
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OrOp = AMDGPU::S_OR_B64;
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XorOp = AMDGPU::S_XOR_B64;
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AndN2Op = AMDGPU::S_ANDN2_B64;
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OrN2Op = AMDGPU::S_ORN2_B64;
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}
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lowerCopiesFromI1();
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lowerPhis();
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lowerCopiesToI1();
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for (unsigned Reg : ConstrainRegs)
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MRI->constrainRegClass(Reg, &AMDGPU::SReg_1_XEXECRegClass);
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ConstrainRegs.clear();
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return true;
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}
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#ifndef NDEBUG
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static bool isVRegCompatibleReg(const SIRegisterInfo &TRI,
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const MachineRegisterInfo &MRI,
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Register Reg) {
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unsigned Size = TRI.getRegSizeInBits(Reg, MRI);
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return Size == 1 || Size == 32;
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}
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#endif
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void SILowerI1Copies::lowerCopiesFromI1() {
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SmallVector<MachineInstr *, 4> DeadCopies;
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for (MachineBasicBlock &MBB : *MF) {
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for (MachineInstr &MI : MBB) {
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if (MI.getOpcode() != AMDGPU::COPY)
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continue;
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Register DstReg = MI.getOperand(0).getReg();
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Register SrcReg = MI.getOperand(1).getReg();
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if (!isVreg1(SrcReg))
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continue;
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if (isLaneMaskReg(DstReg) || isVreg1(DstReg))
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continue;
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// Copy into a 32-bit vector register.
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LLVM_DEBUG(dbgs() << "Lower copy from i1: " << MI);
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DebugLoc DL = MI.getDebugLoc();
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assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg));
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assert(!MI.getOperand(0).getSubReg());
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ConstrainRegs.insert(SrcReg);
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BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
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.addImm(0)
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.addImm(0)
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.addImm(0)
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.addImm(-1)
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.addReg(SrcReg);
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DeadCopies.push_back(&MI);
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}
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for (MachineInstr *MI : DeadCopies)
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MI->eraseFromParent();
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DeadCopies.clear();
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}
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}
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void SILowerI1Copies::lowerPhis() {
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MachineSSAUpdater SSAUpdater(*MF);
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LoopFinder LF(*DT, *PDT);
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PhiIncomingAnalysis PIA(*PDT);
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SmallVector<MachineInstr *, 4> Vreg1Phis;
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SmallVector<MachineBasicBlock *, 4> IncomingBlocks;
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SmallVector<unsigned, 4> IncomingRegs;
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SmallVector<unsigned, 4> IncomingUpdated;
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#ifndef NDEBUG
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DenseSet<unsigned> PhiRegisters;
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#endif
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for (MachineBasicBlock &MBB : *MF) {
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for (MachineInstr &MI : MBB.phis()) {
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if (isVreg1(MI.getOperand(0).getReg()))
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Vreg1Phis.push_back(&MI);
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}
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}
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MachineBasicBlock *PrevMBB = nullptr;
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for (MachineInstr *MI : Vreg1Phis) {
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MachineBasicBlock &MBB = *MI->getParent();
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if (&MBB != PrevMBB) {
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LF.initialize(MBB);
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PrevMBB = &MBB;
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}
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LLVM_DEBUG(dbgs() << "Lower PHI: " << *MI);
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Register DstReg = MI->getOperand(0).getReg();
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MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass
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: &AMDGPU::SReg_64RegClass);
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// Collect incoming values.
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for (unsigned i = 1; i < MI->getNumOperands(); i += 2) {
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assert(i + 1 < MI->getNumOperands());
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Register IncomingReg = MI->getOperand(i).getReg();
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MachineBasicBlock *IncomingMBB = MI->getOperand(i + 1).getMBB();
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MachineInstr *IncomingDef = MRI->getUniqueVRegDef(IncomingReg);
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if (IncomingDef->getOpcode() == AMDGPU::COPY) {
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IncomingReg = IncomingDef->getOperand(1).getReg();
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assert(isLaneMaskReg(IncomingReg) || isVreg1(IncomingReg));
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assert(!IncomingDef->getOperand(1).getSubReg());
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} else if (IncomingDef->getOpcode() == AMDGPU::IMPLICIT_DEF) {
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continue;
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} else {
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assert(IncomingDef->isPHI() || PhiRegisters.count(IncomingReg));
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}
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IncomingBlocks.push_back(IncomingMBB);
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IncomingRegs.push_back(IncomingReg);
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}
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#ifndef NDEBUG
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PhiRegisters.insert(DstReg);
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#endif
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// Phis in a loop that are observed outside the loop receive a simple but
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// conservatively correct treatment.
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std::vector<MachineBasicBlock *> DomBlocks = {&MBB};
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for (MachineInstr &Use : MRI->use_instructions(DstReg))
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DomBlocks.push_back(Use.getParent());
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MachineBasicBlock *PostDomBound =
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PDT->findNearestCommonDominator(DomBlocks);
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unsigned FoundLoopLevel = LF.findLoop(PostDomBound);
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SSAUpdater.Initialize(DstReg);
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if (FoundLoopLevel) {
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LF.addLoopEntries(FoundLoopLevel, SSAUpdater, IncomingBlocks);
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for (unsigned i = 0; i < IncomingRegs.size(); ++i) {
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IncomingUpdated.push_back(createLaneMaskReg(*MF));
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SSAUpdater.AddAvailableValue(IncomingBlocks[i],
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IncomingUpdated.back());
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}
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for (unsigned i = 0; i < IncomingRegs.size(); ++i) {
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MachineBasicBlock &IMBB = *IncomingBlocks[i];
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buildMergeLaneMasks(
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IMBB, getSaluInsertionAtEnd(IMBB), {}, IncomingUpdated[i],
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SSAUpdater.GetValueInMiddleOfBlock(&IMBB), IncomingRegs[i]);
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}
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} else {
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// The phi is not observed from outside a loop. Use a more accurate
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// lowering.
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PIA.analyze(MBB, IncomingBlocks);
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for (MachineBasicBlock *MBB : PIA.predecessors())
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SSAUpdater.AddAvailableValue(MBB, insertUndefLaneMask(*MBB));
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for (unsigned i = 0; i < IncomingRegs.size(); ++i) {
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MachineBasicBlock &IMBB = *IncomingBlocks[i];
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if (PIA.isSource(IMBB)) {
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IncomingUpdated.push_back(0);
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SSAUpdater.AddAvailableValue(&IMBB, IncomingRegs[i]);
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} else {
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IncomingUpdated.push_back(createLaneMaskReg(*MF));
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SSAUpdater.AddAvailableValue(&IMBB, IncomingUpdated.back());
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}
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}
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for (unsigned i = 0; i < IncomingRegs.size(); ++i) {
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if (!IncomingUpdated[i])
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continue;
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MachineBasicBlock &IMBB = *IncomingBlocks[i];
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buildMergeLaneMasks(
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IMBB, getSaluInsertionAtEnd(IMBB), {}, IncomingUpdated[i],
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SSAUpdater.GetValueInMiddleOfBlock(&IMBB), IncomingRegs[i]);
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}
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}
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Register NewReg = SSAUpdater.GetValueInMiddleOfBlock(&MBB);
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if (NewReg != DstReg) {
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MRI->replaceRegWith(NewReg, DstReg);
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MI->eraseFromParent();
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}
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IncomingBlocks.clear();
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IncomingRegs.clear();
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IncomingUpdated.clear();
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}
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}
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void SILowerI1Copies::lowerCopiesToI1() {
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MachineSSAUpdater SSAUpdater(*MF);
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LoopFinder LF(*DT, *PDT);
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SmallVector<MachineInstr *, 4> DeadCopies;
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for (MachineBasicBlock &MBB : *MF) {
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LF.initialize(MBB);
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for (MachineInstr &MI : MBB) {
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if (MI.getOpcode() != AMDGPU::IMPLICIT_DEF &&
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MI.getOpcode() != AMDGPU::COPY)
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continue;
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Register DstReg = MI.getOperand(0).getReg();
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if (!isVreg1(DstReg))
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continue;
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if (MRI->use_empty(DstReg)) {
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DeadCopies.push_back(&MI);
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continue;
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}
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LLVM_DEBUG(dbgs() << "Lower Other: " << MI);
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MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass
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: &AMDGPU::SReg_64RegClass);
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if (MI.getOpcode() == AMDGPU::IMPLICIT_DEF)
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continue;
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DebugLoc DL = MI.getDebugLoc();
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Register SrcReg = MI.getOperand(1).getReg();
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assert(!MI.getOperand(1).getSubReg());
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if (!SrcReg.isVirtual() || (!isLaneMaskReg(SrcReg) && !isVreg1(SrcReg))) {
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assert(TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 32);
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unsigned TmpReg = createLaneMaskReg(*MF);
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BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg)
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.addReg(SrcReg)
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.addImm(0);
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MI.getOperand(1).setReg(TmpReg);
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SrcReg = TmpReg;
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}
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// Defs in a loop that are observed outside the loop must be transformed
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// into appropriate bit manipulation.
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std::vector<MachineBasicBlock *> DomBlocks = {&MBB};
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for (MachineInstr &Use : MRI->use_instructions(DstReg))
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DomBlocks.push_back(Use.getParent());
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MachineBasicBlock *PostDomBound =
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PDT->findNearestCommonDominator(DomBlocks);
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unsigned FoundLoopLevel = LF.findLoop(PostDomBound);
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if (FoundLoopLevel) {
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SSAUpdater.Initialize(DstReg);
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SSAUpdater.AddAvailableValue(&MBB, DstReg);
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LF.addLoopEntries(FoundLoopLevel, SSAUpdater);
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buildMergeLaneMasks(MBB, MI, DL, DstReg,
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SSAUpdater.GetValueInMiddleOfBlock(&MBB), SrcReg);
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DeadCopies.push_back(&MI);
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}
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}
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for (MachineInstr *MI : DeadCopies)
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MI->eraseFromParent();
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DeadCopies.clear();
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}
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}
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bool SILowerI1Copies::isConstantLaneMask(Register Reg, bool &Val) const {
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const MachineInstr *MI;
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for (;;) {
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MI = MRI->getUniqueVRegDef(Reg);
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if (MI->getOpcode() != AMDGPU::COPY)
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break;
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Reg = MI->getOperand(1).getReg();
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if (!Reg.isVirtual())
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return false;
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if (!isLaneMaskReg(Reg))
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return false;
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}
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if (MI->getOpcode() != MovOp)
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return false;
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if (!MI->getOperand(1).isImm())
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return false;
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int64_t Imm = MI->getOperand(1).getImm();
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if (Imm == 0) {
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Val = false;
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return true;
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}
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if (Imm == -1) {
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Val = true;
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return true;
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}
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return false;
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}
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static void instrDefsUsesSCC(const MachineInstr &MI, bool &Def, bool &Use) {
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Def = false;
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Use = false;
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for (const MachineOperand &MO : MI.operands()) {
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if (MO.isReg() && MO.getReg() == AMDGPU::SCC) {
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if (MO.isUse())
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Use = true;
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else
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Def = true;
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}
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}
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}
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/// Return a point at the end of the given \p MBB to insert SALU instructions
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/// for lane mask calculation. Take terminators and SCC into account.
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MachineBasicBlock::iterator
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SILowerI1Copies::getSaluInsertionAtEnd(MachineBasicBlock &MBB) const {
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auto InsertionPt = MBB.getFirstTerminator();
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bool TerminatorsUseSCC = false;
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for (auto I = InsertionPt, E = MBB.end(); I != E; ++I) {
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bool DefsSCC;
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instrDefsUsesSCC(*I, DefsSCC, TerminatorsUseSCC);
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if (TerminatorsUseSCC || DefsSCC)
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break;
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}
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if (!TerminatorsUseSCC)
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return InsertionPt;
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while (InsertionPt != MBB.begin()) {
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InsertionPt--;
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bool DefSCC, UseSCC;
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instrDefsUsesSCC(*InsertionPt, DefSCC, UseSCC);
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if (DefSCC)
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return InsertionPt;
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}
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// We should have at least seen an IMPLICIT_DEF or COPY
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llvm_unreachable("SCC used by terminator but no def in block");
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}
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void SILowerI1Copies::buildMergeLaneMasks(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const DebugLoc &DL, unsigned DstReg,
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unsigned PrevReg, unsigned CurReg) {
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bool PrevVal;
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bool PrevConstant = isConstantLaneMask(PrevReg, PrevVal);
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bool CurVal;
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bool CurConstant = isConstantLaneMask(CurReg, CurVal);
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if (PrevConstant && CurConstant) {
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if (PrevVal == CurVal) {
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BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg);
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} else if (CurVal) {
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BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg);
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} else {
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BuildMI(MBB, I, DL, TII->get(XorOp), DstReg)
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.addReg(ExecReg)
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.addImm(-1);
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}
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return;
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}
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unsigned PrevMaskedReg = 0;
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unsigned CurMaskedReg = 0;
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if (!PrevConstant) {
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if (CurConstant && CurVal) {
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PrevMaskedReg = PrevReg;
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} else {
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PrevMaskedReg = createLaneMaskReg(*MF);
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BuildMI(MBB, I, DL, TII->get(AndN2Op), PrevMaskedReg)
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.addReg(PrevReg)
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.addReg(ExecReg);
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}
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}
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if (!CurConstant) {
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// TODO: check whether CurReg is already masked by EXEC
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if (PrevConstant && PrevVal) {
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CurMaskedReg = CurReg;
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} else {
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CurMaskedReg = createLaneMaskReg(*MF);
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BuildMI(MBB, I, DL, TII->get(AndOp), CurMaskedReg)
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.addReg(CurReg)
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.addReg(ExecReg);
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}
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}
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if (PrevConstant && !PrevVal) {
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BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)
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.addReg(CurMaskedReg);
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} else if (CurConstant && !CurVal) {
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BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)
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.addReg(PrevMaskedReg);
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} else if (PrevConstant && PrevVal) {
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BuildMI(MBB, I, DL, TII->get(OrN2Op), DstReg)
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.addReg(CurMaskedReg)
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.addReg(ExecReg);
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} else {
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BuildMI(MBB, I, DL, TII->get(OrOp), DstReg)
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.addReg(PrevMaskedReg)
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.addReg(CurMaskedReg ? CurMaskedReg : ExecReg);
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}
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}
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