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347 lines
11 KiB
347 lines
11 KiB
//===-- SIPreEmitPeephole.cpp ------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass performs the peephole optimizations before code emission.
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///
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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#define DEBUG_TYPE "si-pre-emit-peephole"
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namespace {
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class SIPreEmitPeephole : public MachineFunctionPass {
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private:
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const SIInstrInfo *TII = nullptr;
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const SIRegisterInfo *TRI = nullptr;
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bool optimizeVccBranch(MachineInstr &MI) const;
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bool optimizeSetGPR(MachineInstr &First, MachineInstr &MI) const;
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public:
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static char ID;
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SIPreEmitPeephole() : MachineFunctionPass(ID) {
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initializeSIPreEmitPeepholePass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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};
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} // End anonymous namespace.
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INITIALIZE_PASS(SIPreEmitPeephole, DEBUG_TYPE,
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"SI peephole optimizations", false, false)
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char SIPreEmitPeephole::ID = 0;
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char &llvm::SIPreEmitPeepholeID = SIPreEmitPeephole::ID;
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bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const {
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// Match:
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// sreg = -1 or 0
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// vcc = S_AND_B64 exec, sreg or S_ANDN2_B64 exec, sreg
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// S_CBRANCH_VCC[N]Z
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// =>
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// S_CBRANCH_EXEC[N]Z
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// We end up with this pattern sometimes after basic block placement.
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// It happens while combining a block which assigns -1 or 0 to a saved mask
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// and another block which consumes that saved mask and then a branch.
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bool Changed = false;
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MachineBasicBlock &MBB = *MI.getParent();
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const GCNSubtarget &ST = MBB.getParent()->getSubtarget<GCNSubtarget>();
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const bool IsWave32 = ST.isWave32();
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const unsigned CondReg = TRI->getVCC();
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const unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
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const unsigned And = IsWave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
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const unsigned AndN2 = IsWave32 ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_ANDN2_B64;
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const unsigned Mov = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
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MachineBasicBlock::reverse_iterator A = MI.getReverseIterator(),
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E = MBB.rend();
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bool ReadsCond = false;
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unsigned Threshold = 5;
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for (++A; A != E; ++A) {
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if (!--Threshold)
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return false;
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if (A->modifiesRegister(ExecReg, TRI))
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return false;
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if (A->modifiesRegister(CondReg, TRI)) {
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if (!A->definesRegister(CondReg, TRI) ||
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(A->getOpcode() != And && A->getOpcode() != AndN2))
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return false;
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break;
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}
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ReadsCond |= A->readsRegister(CondReg, TRI);
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}
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if (A == E)
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return false;
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MachineOperand &Op1 = A->getOperand(1);
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MachineOperand &Op2 = A->getOperand(2);
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if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) {
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TII->commuteInstruction(*A);
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Changed = true;
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}
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if (Op1.getReg() != ExecReg)
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return Changed;
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if (Op2.isImm() && !(Op2.getImm() == -1 || Op2.getImm() == 0))
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return Changed;
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int64_t MaskValue = 0;
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Register SReg;
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if (Op2.isReg()) {
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SReg = Op2.getReg();
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auto M = std::next(A);
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bool ReadsSreg = false;
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for (; M != E; ++M) {
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if (M->definesRegister(SReg, TRI))
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break;
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if (M->modifiesRegister(SReg, TRI))
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return Changed;
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ReadsSreg |= M->readsRegister(SReg, TRI);
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}
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if (M == E || !M->isMoveImmediate() || !M->getOperand(1).isImm() ||
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(M->getOperand(1).getImm() != -1 && M->getOperand(1).getImm() != 0))
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return Changed;
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MaskValue = M->getOperand(1).getImm();
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// First if sreg is only used in the AND instruction fold the immediate
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// into into the AND.
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if (!ReadsSreg && Op2.isKill()) {
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A->getOperand(2).ChangeToImmediate(MaskValue);
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M->eraseFromParent();
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}
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} else if (Op2.isImm()) {
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MaskValue = Op2.getImm();
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} else {
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llvm_unreachable("Op2 must be register or immediate");
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}
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// Invert mask for s_andn2
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assert(MaskValue == 0 || MaskValue == -1);
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if (A->getOpcode() == AndN2)
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MaskValue = ~MaskValue;
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if (!ReadsCond && A->registerDefIsDead(AMDGPU::SCC)) {
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if (!MI.killsRegister(CondReg, TRI)) {
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// Replace AND with MOV
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if (MaskValue == 0) {
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BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg)
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.addImm(0);
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} else {
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BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg)
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.addReg(ExecReg);
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}
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}
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// Remove AND instruction
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A->eraseFromParent();
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}
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bool IsVCCZ = MI.getOpcode() == AMDGPU::S_CBRANCH_VCCZ;
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if (SReg == ExecReg) {
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// EXEC is updated directly
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if (IsVCCZ) {
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MI.eraseFromParent();
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return true;
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}
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MI.setDesc(TII->get(AMDGPU::S_BRANCH));
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} else if (IsVCCZ && MaskValue == 0) {
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// Will always branch
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// Remove all succesors shadowed by new unconditional branch
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MachineBasicBlock *Parent = MI.getParent();
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SmallVector<MachineInstr *, 4> ToRemove;
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bool Found = false;
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for (MachineInstr &Term : Parent->terminators()) {
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if (Found) {
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if (Term.isBranch())
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ToRemove.push_back(&Term);
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} else {
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Found = Term.isIdenticalTo(MI);
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}
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}
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assert(Found && "conditional branch is not terminator");
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for (auto BranchMI : ToRemove) {
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MachineOperand &Dst = BranchMI->getOperand(0);
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assert(Dst.isMBB() && "destination is not basic block");
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Parent->removeSuccessor(Dst.getMBB());
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BranchMI->eraseFromParent();
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}
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if (MachineBasicBlock *Succ = Parent->getFallThrough()) {
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Parent->removeSuccessor(Succ);
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}
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// Rewrite to unconditional branch
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MI.setDesc(TII->get(AMDGPU::S_BRANCH));
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} else if (!IsVCCZ && MaskValue == 0) {
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// Will never branch
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MachineOperand &Dst = MI.getOperand(0);
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assert(Dst.isMBB() && "destination is not basic block");
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MI.getParent()->removeSuccessor(Dst.getMBB());
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MI.eraseFromParent();
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return true;
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} else if (MaskValue == -1) {
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// Depends only on EXEC
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MI.setDesc(
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TII->get(IsVCCZ ? AMDGPU::S_CBRANCH_EXECZ : AMDGPU::S_CBRANCH_EXECNZ));
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}
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MI.RemoveOperand(MI.findRegisterUseOperandIdx(CondReg, false /*Kill*/, TRI));
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MI.addImplicitDefUseOperands(*MBB.getParent());
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return true;
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}
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bool SIPreEmitPeephole::optimizeSetGPR(MachineInstr &First,
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MachineInstr &MI) const {
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MachineBasicBlock &MBB = *MI.getParent();
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const MachineFunction &MF = *MBB.getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
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Register IdxReg = Idx->isReg() ? Idx->getReg() : Register();
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SmallVector<MachineInstr *, 4> ToRemove;
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bool IdxOn = true;
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if (!MI.isIdenticalTo(First))
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return false;
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// Scan back to find an identical S_SET_GPR_IDX_ON
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for (MachineBasicBlock::iterator I = std::next(First.getIterator()),
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E = MI.getIterator(); I != E; ++I) {
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switch (I->getOpcode()) {
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case AMDGPU::S_SET_GPR_IDX_MODE:
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return false;
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case AMDGPU::S_SET_GPR_IDX_OFF:
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IdxOn = false;
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ToRemove.push_back(&*I);
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break;
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default:
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if (I->modifiesRegister(AMDGPU::M0, TRI))
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return false;
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if (IdxReg && I->modifiesRegister(IdxReg, TRI))
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return false;
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if (llvm::any_of(I->operands(),
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[&MRI, this](const MachineOperand &MO) {
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return MO.isReg() &&
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TRI->isVectorRegister(MRI, MO.getReg());
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})) {
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// The only exception allowed here is another indirect vector move
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// with the same mode.
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if (!IdxOn ||
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!((I->getOpcode() == AMDGPU::V_MOV_B32_e32 &&
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I->hasRegisterImplicitUseOperand(AMDGPU::M0)) ||
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I->getOpcode() == AMDGPU::V_MOV_B32_indirect))
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return false;
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}
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}
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}
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MI.eraseFromParent();
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for (MachineInstr *RI : ToRemove)
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RI->eraseFromParent();
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return true;
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}
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bool SIPreEmitPeephole::runOnMachineFunction(MachineFunction &MF) {
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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TII = ST.getInstrInfo();
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TRI = &TII->getRegisterInfo();
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MachineBasicBlock *EmptyMBBAtEnd = nullptr;
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF) {
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MachineBasicBlock::iterator MBBE = MBB.getFirstTerminator();
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MachineBasicBlock::iterator TermI = MBBE;
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// Check first terminator for VCC branches to optimize
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if (TermI != MBB.end()) {
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MachineInstr &MI = *TermI;
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switch (MI.getOpcode()) {
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case AMDGPU::S_CBRANCH_VCCZ:
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case AMDGPU::S_CBRANCH_VCCNZ:
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Changed |= optimizeVccBranch(MI);
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continue;
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default:
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break;
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}
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}
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// Check all terminators for SI_RETURN_TO_EPILOG
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// FIXME: This is not an optimization and should be moved somewhere else.
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while (TermI != MBB.end()) {
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MachineInstr &MI = *TermI;
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if (MI.getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
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assert(!MF.getInfo<SIMachineFunctionInfo>()->returnsVoid());
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// Graphics shaders returning non-void shouldn't contain S_ENDPGM,
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// because external bytecode will be appended at the end.
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if (&MBB != &MF.back() || &MI != &MBB.back()) {
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// SI_RETURN_TO_EPILOG is not the last instruction. Add an empty block
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// at the end and jump there.
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if (!EmptyMBBAtEnd) {
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EmptyMBBAtEnd = MF.CreateMachineBasicBlock();
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MF.insert(MF.end(), EmptyMBBAtEnd);
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}
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MBB.addSuccessor(EmptyMBBAtEnd);
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BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(AMDGPU::S_BRANCH))
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.addMBB(EmptyMBBAtEnd);
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MI.eraseFromParent();
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MBBE = MBB.getFirstTerminator();
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TermI = MBBE;
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continue;
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}
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}
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TermI++;
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}
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if (!ST.hasVGPRIndexMode())
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continue;
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MachineInstr *SetGPRMI = nullptr;
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const unsigned Threshold = 20;
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unsigned Count = 0;
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// Scan the block for two S_SET_GPR_IDX_ON instructions to see if a
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// second is not needed. Do expensive checks in the optimizeSetGPR()
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// and limit the distance to 20 instructions for compile time purposes.
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for (MachineBasicBlock::iterator MBBI = MBB.begin(); MBBI != MBBE; ) {
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MachineInstr &MI = *MBBI;
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++MBBI;
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if (Count == Threshold)
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SetGPRMI = nullptr;
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else
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++Count;
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if (MI.getOpcode() != AMDGPU::S_SET_GPR_IDX_ON)
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continue;
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Count = 0;
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if (!SetGPRMI) {
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SetGPRMI = &MI;
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continue;
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}
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if (optimizeSetGPR(*SetGPRMI, MI))
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Changed = true;
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else
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SetGPRMI = &MI;
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}
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}
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return Changed;
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}
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