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420 lines
16 KiB
420 lines
16 KiB
//===-- NVPTXTargetTransformInfo.cpp - NVPTX specific TTI -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTXTargetTransformInfo.h"
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#include "NVPTXUtilities.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/CodeGen/CostTable.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/IR/IntrinsicsNVPTX.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "NVPTXtti"
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// Whether the given intrinsic reads threadIdx.x/y/z.
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static bool readsThreadIndex(const IntrinsicInst *II) {
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switch (II->getIntrinsicID()) {
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default: return false;
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case Intrinsic::nvvm_read_ptx_sreg_tid_x:
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case Intrinsic::nvvm_read_ptx_sreg_tid_y:
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case Intrinsic::nvvm_read_ptx_sreg_tid_z:
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return true;
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}
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}
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static bool readsLaneId(const IntrinsicInst *II) {
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return II->getIntrinsicID() == Intrinsic::nvvm_read_ptx_sreg_laneid;
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}
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// Whether the given intrinsic is an atomic instruction in PTX.
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static bool isNVVMAtomic(const IntrinsicInst *II) {
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switch (II->getIntrinsicID()) {
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default: return false;
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case Intrinsic::nvvm_atomic_load_inc_32:
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case Intrinsic::nvvm_atomic_load_dec_32:
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case Intrinsic::nvvm_atomic_add_gen_f_cta:
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case Intrinsic::nvvm_atomic_add_gen_f_sys:
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case Intrinsic::nvvm_atomic_add_gen_i_cta:
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case Intrinsic::nvvm_atomic_add_gen_i_sys:
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case Intrinsic::nvvm_atomic_and_gen_i_cta:
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case Intrinsic::nvvm_atomic_and_gen_i_sys:
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case Intrinsic::nvvm_atomic_cas_gen_i_cta:
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case Intrinsic::nvvm_atomic_cas_gen_i_sys:
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case Intrinsic::nvvm_atomic_dec_gen_i_cta:
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case Intrinsic::nvvm_atomic_dec_gen_i_sys:
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case Intrinsic::nvvm_atomic_inc_gen_i_cta:
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case Intrinsic::nvvm_atomic_inc_gen_i_sys:
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case Intrinsic::nvvm_atomic_max_gen_i_cta:
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case Intrinsic::nvvm_atomic_max_gen_i_sys:
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case Intrinsic::nvvm_atomic_min_gen_i_cta:
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case Intrinsic::nvvm_atomic_min_gen_i_sys:
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case Intrinsic::nvvm_atomic_or_gen_i_cta:
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case Intrinsic::nvvm_atomic_or_gen_i_sys:
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case Intrinsic::nvvm_atomic_exch_gen_i_cta:
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case Intrinsic::nvvm_atomic_exch_gen_i_sys:
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case Intrinsic::nvvm_atomic_xor_gen_i_cta:
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case Intrinsic::nvvm_atomic_xor_gen_i_sys:
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return true;
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}
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}
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bool NVPTXTTIImpl::isSourceOfDivergence(const Value *V) {
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// Without inter-procedural analysis, we conservatively assume that arguments
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// to __device__ functions are divergent.
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if (const Argument *Arg = dyn_cast<Argument>(V))
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return !isKernelFunction(*Arg->getParent());
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if (const Instruction *I = dyn_cast<Instruction>(V)) {
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// Without pointer analysis, we conservatively assume values loaded from
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// generic or local address space are divergent.
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if (const LoadInst *LI = dyn_cast<LoadInst>(I)) {
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unsigned AS = LI->getPointerAddressSpace();
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return AS == ADDRESS_SPACE_GENERIC || AS == ADDRESS_SPACE_LOCAL;
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}
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// Atomic instructions may cause divergence. Atomic instructions are
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// executed sequentially across all threads in a warp. Therefore, an earlier
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// executed thread may see different memory inputs than a later executed
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// thread. For example, suppose *a = 0 initially.
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//
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// atom.global.add.s32 d, [a], 1
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//
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// returns 0 for the first thread that enters the critical region, and 1 for
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// the second thread.
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if (I->isAtomic())
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return true;
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if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
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// Instructions that read threadIdx are obviously divergent.
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if (readsThreadIndex(II) || readsLaneId(II))
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return true;
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// Handle the NVPTX atomic instrinsics that cannot be represented as an
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// atomic IR instruction.
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if (isNVVMAtomic(II))
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return true;
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}
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// Conservatively consider the return value of function calls as divergent.
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// We could analyze callees with bodies more precisely using
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// inter-procedural analysis.
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if (isa<CallInst>(I))
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return true;
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}
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return false;
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}
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// Convert NVVM intrinsics to target-generic LLVM code where possible.
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static Instruction *simplifyNvvmIntrinsic(IntrinsicInst *II, InstCombiner &IC) {
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// Each NVVM intrinsic we can simplify can be replaced with one of:
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//
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// * an LLVM intrinsic,
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// * an LLVM cast operation,
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// * an LLVM binary operation, or
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// * ad-hoc LLVM IR for the particular operation.
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// Some transformations are only valid when the module's
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// flush-denormals-to-zero (ftz) setting is true/false, whereas other
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// transformations are valid regardless of the module's ftz setting.
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enum FtzRequirementTy {
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FTZ_Any, // Any ftz setting is ok.
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FTZ_MustBeOn, // Transformation is valid only if ftz is on.
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FTZ_MustBeOff, // Transformation is valid only if ftz is off.
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};
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// Classes of NVVM intrinsics that can't be replaced one-to-one with a
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// target-generic intrinsic, cast op, or binary op but that we can nonetheless
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// simplify.
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enum SpecialCase {
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SPC_Reciprocal,
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};
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// SimplifyAction is a poor-man's variant (plus an additional flag) that
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// represents how to replace an NVVM intrinsic with target-generic LLVM IR.
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struct SimplifyAction {
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// Invariant: At most one of these Optionals has a value.
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Optional<Intrinsic::ID> IID;
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Optional<Instruction::CastOps> CastOp;
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Optional<Instruction::BinaryOps> BinaryOp;
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Optional<SpecialCase> Special;
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FtzRequirementTy FtzRequirement = FTZ_Any;
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SimplifyAction() = default;
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SimplifyAction(Intrinsic::ID IID, FtzRequirementTy FtzReq)
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: IID(IID), FtzRequirement(FtzReq) {}
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// Cast operations don't have anything to do with FTZ, so we skip that
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// argument.
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SimplifyAction(Instruction::CastOps CastOp) : CastOp(CastOp) {}
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SimplifyAction(Instruction::BinaryOps BinaryOp, FtzRequirementTy FtzReq)
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: BinaryOp(BinaryOp), FtzRequirement(FtzReq) {}
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SimplifyAction(SpecialCase Special, FtzRequirementTy FtzReq)
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: Special(Special), FtzRequirement(FtzReq) {}
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};
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// Try to generate a SimplifyAction describing how to replace our
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// IntrinsicInstr with target-generic LLVM IR.
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const SimplifyAction Action = [II]() -> SimplifyAction {
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switch (II->getIntrinsicID()) {
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// NVVM intrinsics that map directly to LLVM intrinsics.
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case Intrinsic::nvvm_ceil_d:
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return {Intrinsic::ceil, FTZ_Any};
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case Intrinsic::nvvm_ceil_f:
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return {Intrinsic::ceil, FTZ_MustBeOff};
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case Intrinsic::nvvm_ceil_ftz_f:
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return {Intrinsic::ceil, FTZ_MustBeOn};
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case Intrinsic::nvvm_fabs_d:
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return {Intrinsic::fabs, FTZ_Any};
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case Intrinsic::nvvm_fabs_f:
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return {Intrinsic::fabs, FTZ_MustBeOff};
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case Intrinsic::nvvm_fabs_ftz_f:
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return {Intrinsic::fabs, FTZ_MustBeOn};
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case Intrinsic::nvvm_floor_d:
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return {Intrinsic::floor, FTZ_Any};
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case Intrinsic::nvvm_floor_f:
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return {Intrinsic::floor, FTZ_MustBeOff};
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case Intrinsic::nvvm_floor_ftz_f:
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return {Intrinsic::floor, FTZ_MustBeOn};
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case Intrinsic::nvvm_fma_rn_d:
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return {Intrinsic::fma, FTZ_Any};
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case Intrinsic::nvvm_fma_rn_f:
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return {Intrinsic::fma, FTZ_MustBeOff};
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case Intrinsic::nvvm_fma_rn_ftz_f:
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return {Intrinsic::fma, FTZ_MustBeOn};
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case Intrinsic::nvvm_fmax_d:
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return {Intrinsic::maxnum, FTZ_Any};
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case Intrinsic::nvvm_fmax_f:
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return {Intrinsic::maxnum, FTZ_MustBeOff};
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case Intrinsic::nvvm_fmax_ftz_f:
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return {Intrinsic::maxnum, FTZ_MustBeOn};
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case Intrinsic::nvvm_fmin_d:
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return {Intrinsic::minnum, FTZ_Any};
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case Intrinsic::nvvm_fmin_f:
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return {Intrinsic::minnum, FTZ_MustBeOff};
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case Intrinsic::nvvm_fmin_ftz_f:
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return {Intrinsic::minnum, FTZ_MustBeOn};
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case Intrinsic::nvvm_round_d:
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return {Intrinsic::round, FTZ_Any};
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case Intrinsic::nvvm_round_f:
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return {Intrinsic::round, FTZ_MustBeOff};
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case Intrinsic::nvvm_round_ftz_f:
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return {Intrinsic::round, FTZ_MustBeOn};
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case Intrinsic::nvvm_sqrt_rn_d:
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return {Intrinsic::sqrt, FTZ_Any};
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case Intrinsic::nvvm_sqrt_f:
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// nvvm_sqrt_f is a special case. For most intrinsics, foo_ftz_f is the
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// ftz version, and foo_f is the non-ftz version. But nvvm_sqrt_f adopts
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// the ftz-ness of the surrounding code. sqrt_rn_f and sqrt_rn_ftz_f are
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// the versions with explicit ftz-ness.
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return {Intrinsic::sqrt, FTZ_Any};
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case Intrinsic::nvvm_sqrt_rn_f:
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return {Intrinsic::sqrt, FTZ_MustBeOff};
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case Intrinsic::nvvm_sqrt_rn_ftz_f:
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return {Intrinsic::sqrt, FTZ_MustBeOn};
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case Intrinsic::nvvm_trunc_d:
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return {Intrinsic::trunc, FTZ_Any};
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case Intrinsic::nvvm_trunc_f:
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return {Intrinsic::trunc, FTZ_MustBeOff};
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case Intrinsic::nvvm_trunc_ftz_f:
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return {Intrinsic::trunc, FTZ_MustBeOn};
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// NVVM intrinsics that map to LLVM cast operations.
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//
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// Note that llvm's target-generic conversion operators correspond to the rz
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// (round to zero) versions of the nvvm conversion intrinsics, even though
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// most everything else here uses the rn (round to nearest even) nvvm ops.
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case Intrinsic::nvvm_d2i_rz:
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case Intrinsic::nvvm_f2i_rz:
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case Intrinsic::nvvm_d2ll_rz:
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case Intrinsic::nvvm_f2ll_rz:
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return {Instruction::FPToSI};
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case Intrinsic::nvvm_d2ui_rz:
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case Intrinsic::nvvm_f2ui_rz:
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case Intrinsic::nvvm_d2ull_rz:
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case Intrinsic::nvvm_f2ull_rz:
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return {Instruction::FPToUI};
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case Intrinsic::nvvm_i2d_rz:
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case Intrinsic::nvvm_i2f_rz:
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case Intrinsic::nvvm_ll2d_rz:
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case Intrinsic::nvvm_ll2f_rz:
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return {Instruction::SIToFP};
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case Intrinsic::nvvm_ui2d_rz:
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case Intrinsic::nvvm_ui2f_rz:
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case Intrinsic::nvvm_ull2d_rz:
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case Intrinsic::nvvm_ull2f_rz:
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return {Instruction::UIToFP};
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// NVVM intrinsics that map to LLVM binary ops.
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case Intrinsic::nvvm_add_rn_d:
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return {Instruction::FAdd, FTZ_Any};
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case Intrinsic::nvvm_add_rn_f:
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return {Instruction::FAdd, FTZ_MustBeOff};
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case Intrinsic::nvvm_add_rn_ftz_f:
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return {Instruction::FAdd, FTZ_MustBeOn};
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case Intrinsic::nvvm_mul_rn_d:
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return {Instruction::FMul, FTZ_Any};
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case Intrinsic::nvvm_mul_rn_f:
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return {Instruction::FMul, FTZ_MustBeOff};
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case Intrinsic::nvvm_mul_rn_ftz_f:
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return {Instruction::FMul, FTZ_MustBeOn};
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case Intrinsic::nvvm_div_rn_d:
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return {Instruction::FDiv, FTZ_Any};
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case Intrinsic::nvvm_div_rn_f:
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return {Instruction::FDiv, FTZ_MustBeOff};
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case Intrinsic::nvvm_div_rn_ftz_f:
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return {Instruction::FDiv, FTZ_MustBeOn};
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// The remainder of cases are NVVM intrinsics that map to LLVM idioms, but
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// need special handling.
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//
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// We seem to be missing intrinsics for rcp.approx.{ftz.}f32, which is just
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// as well.
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case Intrinsic::nvvm_rcp_rn_d:
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return {SPC_Reciprocal, FTZ_Any};
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case Intrinsic::nvvm_rcp_rn_f:
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return {SPC_Reciprocal, FTZ_MustBeOff};
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case Intrinsic::nvvm_rcp_rn_ftz_f:
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return {SPC_Reciprocal, FTZ_MustBeOn};
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// We do not currently simplify intrinsics that give an approximate
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// answer. These include:
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//
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// - nvvm_cos_approx_{f,ftz_f}
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// - nvvm_ex2_approx_{d,f,ftz_f}
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// - nvvm_lg2_approx_{d,f,ftz_f}
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// - nvvm_sin_approx_{f,ftz_f}
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// - nvvm_sqrt_approx_{f,ftz_f}
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// - nvvm_rsqrt_approx_{d,f,ftz_f}
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// - nvvm_div_approx_{ftz_d,ftz_f,f}
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// - nvvm_rcp_approx_ftz_d
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//
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// Ideally we'd encode them as e.g. "fast call @llvm.cos", where "fast"
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// means that fastmath is enabled in the intrinsic. Unfortunately only
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// binary operators (currently) have a fastmath bit in SelectionDAG, so
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// this information gets lost and we can't select on it.
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//
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// TODO: div and rcp are lowered to a binary op, so these we could in
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// theory lower them to "fast fdiv".
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default:
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return {};
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}
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}();
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// If Action.FtzRequirementTy is not satisfied by the module's ftz state, we
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// can bail out now. (Notice that in the case that IID is not an NVVM
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// intrinsic, we don't have to look up any module metadata, as
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// FtzRequirementTy will be FTZ_Any.)
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if (Action.FtzRequirement != FTZ_Any) {
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StringRef Attr = II->getFunction()
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->getFnAttribute("denormal-fp-math-f32")
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.getValueAsString();
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DenormalMode Mode = parseDenormalFPAttribute(Attr);
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bool FtzEnabled = Mode.Output != DenormalMode::IEEE;
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if (FtzEnabled != (Action.FtzRequirement == FTZ_MustBeOn))
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return nullptr;
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}
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// Simplify to target-generic intrinsic.
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if (Action.IID) {
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SmallVector<Value *, 4> Args(II->arg_operands());
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// All the target-generic intrinsics currently of interest to us have one
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// type argument, equal to that of the nvvm intrinsic's argument.
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Type *Tys[] = {II->getArgOperand(0)->getType()};
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return CallInst::Create(
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Intrinsic::getDeclaration(II->getModule(), *Action.IID, Tys), Args);
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}
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// Simplify to target-generic binary op.
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if (Action.BinaryOp)
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return BinaryOperator::Create(*Action.BinaryOp, II->getArgOperand(0),
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II->getArgOperand(1), II->getName());
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// Simplify to target-generic cast op.
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if (Action.CastOp)
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return CastInst::Create(*Action.CastOp, II->getArgOperand(0), II->getType(),
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II->getName());
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// All that's left are the special cases.
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if (!Action.Special)
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return nullptr;
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switch (*Action.Special) {
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case SPC_Reciprocal:
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// Simplify reciprocal.
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return BinaryOperator::Create(
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Instruction::FDiv, ConstantFP::get(II->getArgOperand(0)->getType(), 1),
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II->getArgOperand(0), II->getName());
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}
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llvm_unreachable("All SpecialCase enumerators should be handled in switch.");
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}
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Optional<Instruction *>
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NVPTXTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
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if (Instruction *I = simplifyNvvmIntrinsic(&II, IC)) {
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return I;
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}
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return None;
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}
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int NVPTXTTIImpl::getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
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TTI::OperandValueKind Opd1Info,
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TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
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TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args,
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const Instruction *CxtI) {
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// Legalize the type.
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std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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switch (ISD) {
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default:
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return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info,
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Opd2Info,
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Opd1PropInfo, Opd2PropInfo);
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case ISD::ADD:
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case ISD::MUL:
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case ISD::XOR:
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case ISD::OR:
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case ISD::AND:
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// The machine code (SASS) simulates an i64 with two i32. Therefore, we
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// estimate that arithmetic operations on i64 are twice as expensive as
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// those on types that can fit into one machine register.
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if (LT.second.SimpleTy == MVT::i64)
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return 2 * LT.first;
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// Delegate other cases to the basic TTI.
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return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info,
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Opd2Info,
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Opd1PropInfo, Opd2PropInfo);
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}
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}
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void NVPTXTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP) {
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BaseT::getUnrollingPreferences(L, SE, UP);
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// Enable partial unrolling and runtime unrolling, but reduce the
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// threshold. This partially unrolls small loops which are often
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// unrolled by the PTX to SASS compiler and unrolling earlier can be
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// beneficial.
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UP.Partial = UP.Runtime = true;
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UP.PartialThreshold = UP.Threshold / 4;
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}
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void NVPTXTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP) {
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BaseT::getPeelingPreferences(L, SE, PP);
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}
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