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146 lines
4.9 KiB
146 lines
4.9 KiB
//===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides X86 specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
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#define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
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#include <memory>
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#include <string>
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namespace llvm {
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class formatted_raw_ostream;
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInst;
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class MCInstPrinter;
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class MCInstrInfo;
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class MCObjectTargetWriter;
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class MCObjectWriter;
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class MCRegister;
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class MCRegisterInfo;
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class MCStreamer;
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class MCSubtargetInfo;
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class MCTargetOptions;
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class MCTargetStreamer;
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class Target;
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class Triple;
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class StringRef;
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/// Flavour of dwarf regnumbers
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///
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namespace DWARFFlavour {
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enum {
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X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
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};
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}
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/// Native X86 register numbers
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///
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namespace N86 {
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enum {
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EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
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};
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}
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namespace X86_MC {
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std::string ParseX86Triple(const Triple &TT);
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unsigned getDwarfRegFlavour(const Triple &TT, bool isEH);
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void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI);
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/// Returns true if this instruction has a LOCK prefix.
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bool hasLockPrefix(const MCInst &MI);
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/// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc.
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/// do not need to go through TargetRegistry.
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MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
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StringRef FS);
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}
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MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx);
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MCAsmBackend *createX86_32AsmBackend(const Target &T,
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const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options);
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MCAsmBackend *createX86_64AsmBackend(const Target &T,
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const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options);
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/// Implements X86-only directives for assembly emission.
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MCTargetStreamer *createX86AsmTargetStreamer(MCStreamer &S,
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formatted_raw_ostream &OS,
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MCInstPrinter *InstPrinter,
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bool IsVerboseAsm);
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/// Implements X86-only directives for object files.
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MCTargetStreamer *createX86ObjectTargetStreamer(MCStreamer &S,
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const MCSubtargetInfo &STI);
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/// Construct an X86 Windows COFF machine code streamer which will generate
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/// PE/COFF format object files.
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///
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/// Takes ownership of \p AB and \p CE.
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MCStreamer *createX86WinCOFFStreamer(MCContext &C,
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std::unique_ptr<MCAsmBackend> &&AB,
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std::unique_ptr<MCObjectWriter> &&OW,
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std::unique_ptr<MCCodeEmitter> &&CE,
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bool RelaxAll,
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bool IncrementalLinkerCompatible);
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/// Construct an X86 Mach-O object writer.
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std::unique_ptr<MCObjectTargetWriter>
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createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype);
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/// Construct an X86 ELF object writer.
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std::unique_ptr<MCObjectTargetWriter>
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createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine);
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/// Construct an X86 Win COFF object writer.
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std::unique_ptr<MCObjectTargetWriter>
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createX86WinCOFFObjectWriter(bool Is64Bit);
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/// Returns the sub or super register of a specific X86 register.
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/// e.g. getX86SubSuperRegister(X86::EAX, 16) returns X86::AX.
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/// Aborts on error.
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MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false);
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/// Returns the sub or super register of a specific X86 register.
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/// Like getX86SubSuperRegister() but returns 0 on error.
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MCRegister getX86SubSuperRegisterOrZero(MCRegister, unsigned,
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bool High = false);
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} // End llvm namespace
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// Defines symbolic names for X86 registers. This defines a mapping from
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// register name to register number.
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//
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#define GET_REGINFO_ENUM
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#include "X86GenRegisterInfo.inc"
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// Defines symbolic names for the X86 instructions.
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//
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#define GET_INSTRINFO_ENUM
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#define GET_INSTRINFO_MC_HELPER_DECLS
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#include "X86GenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "X86GenSubtargetInfo.inc"
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#endif
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