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249 lines
8.2 KiB
249 lines
8.2 KiB
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -amdgpu-global-isel-risky-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
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; Make sure the branch targets are correct after lowering llvm.amdgcn.if
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define i32 @divergent_if_swap_brtarget_order0(i32 %value) {
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; CHECK-LABEL: divergent_if_swap_brtarget_order0:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; CHECK-NEXT: ; implicit-def: $vgpr0
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; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; CHECK-NEXT: s_cbranch_execz BB0_2
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; CHECK-NEXT: ; %bb.1: ; %if.true
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; CHECK-NEXT: global_load_dword v0, v[0:1], off
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; CHECK-NEXT: BB0_2: ; %endif
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; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%c = icmp ne i32 %value, 0
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br i1 %c, label %if.true, label %endif
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if.true:
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%val = load volatile i32, i32 addrspace(1)* undef
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br label %endif
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endif:
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%v = phi i32 [ %val, %if.true ], [ undef, %entry ]
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ret i32 %v
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}
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define i32 @divergent_if_swap_brtarget_order1(i32 %value) {
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; CHECK-LABEL: divergent_if_swap_brtarget_order1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; CHECK-NEXT: ; implicit-def: $vgpr0
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; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; CHECK-NEXT: s_cbranch_execz BB1_2
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; CHECK-NEXT: ; %bb.1: ; %if.true
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; CHECK-NEXT: global_load_dword v0, v[0:1], off
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; CHECK-NEXT: BB1_2: ; %endif
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; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%c = icmp ne i32 %value, 0
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br i1 %c, label %if.true, label %endif
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endif:
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%v = phi i32 [ %val, %if.true ], [ undef, %entry ]
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ret i32 %v
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if.true:
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%val = load volatile i32, i32 addrspace(1)* undef
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br label %endif
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}
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; Make sure and 1 is inserted on llvm.amdgcn.if
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define i32 @divergent_if_nonboolean_condition0(i32 %value) {
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; CHECK-LABEL: divergent_if_nonboolean_condition0:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; CHECK-NEXT: ; implicit-def: $vgpr0
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; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; CHECK-NEXT: s_cbranch_execz BB2_2
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; CHECK-NEXT: ; %bb.1: ; %if.true
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; CHECK-NEXT: global_load_dword v0, v[0:1], off
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; CHECK-NEXT: BB2_2: ; %endif
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; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%c = trunc i32 %value to i1
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br i1 %c, label %if.true, label %endif
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if.true:
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%val = load volatile i32, i32 addrspace(1)* undef
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br label %endif
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endif:
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%v = phi i32 [ %val, %if.true ], [ undef, %entry ]
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ret i32 %v
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}
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; Make sure and 1 is inserted on llvm.amdgcn.if
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define i32 @divergent_if_nonboolean_condition1(i32 addrspace(1)* %ptr) {
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; CHECK-LABEL: divergent_if_nonboolean_condition1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: global_load_dword v0, v[0:1], off
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; CHECK-NEXT: ; implicit-def: $vgpr0
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; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; CHECK-NEXT: s_cbranch_execz BB3_2
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; CHECK-NEXT: ; %bb.1: ; %if.true
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; CHECK-NEXT: global_load_dword v0, v[0:1], off
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; CHECK-NEXT: BB3_2: ; %endif
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; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%value = load i32, i32 addrspace(1)* %ptr
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%c = trunc i32 %value to i1
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br i1 %c, label %if.true, label %endif
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if.true:
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%val = load volatile i32, i32 addrspace(1)* undef
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br label %endif
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endif:
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%v = phi i32 [ %val, %if.true ], [ undef, %entry ]
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ret i32 %v
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}
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@external_constant = external addrspace(4) constant i32, align 4
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@const.ptr = external addrspace(4) constant float*, align 4
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; Make sure this case compiles. G_ICMP was mis-mapped due to having
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; the result register class constrained by llvm.amdgcn.if lowering.
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define void @constrained_if_register_class() {
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; CHECK-LABEL: constrained_if_register_class:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_getpc_b64 s[4:5]
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; CHECK-NEXT: s_add_u32 s4, s4, external_constant@gotpcrel32@lo+4
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; CHECK-NEXT: s_addc_u32 s5, s5, external_constant@gotpcrel32@hi+12
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; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_load_dword s4, s[4:5], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_cmp_lg_u32 s4, 0
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; CHECK-NEXT: s_cselect_b32 s4, 1, 0
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; CHECK-NEXT: s_and_b32 s4, s4, 1
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; CHECK-NEXT: s_cmp_lg_u32 s4, 0
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; CHECK-NEXT: s_cbranch_scc1 BB4_4
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; CHECK-NEXT: ; %bb.1: ; %bb2
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; CHECK-NEXT: s_getpc_b64 s[6:7]
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; CHECK-NEXT: s_add_u32 s6, s6, const.ptr@gotpcrel32@lo+4
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; CHECK-NEXT: s_addc_u32 s7, s7, const.ptr@gotpcrel32@hi+12
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; CHECK-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: s_mov_b32 s4, -1
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: global_load_dword v0, v0, s[6:7]
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, 1.0, v0
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; CHECK-NEXT: s_cbranch_vccnz BB4_3
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; CHECK-NEXT: ; %bb.2: ; %bb7
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; CHECK-NEXT: s_mov_b32 s4, 0
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; CHECK-NEXT: BB4_3: ; %bb8
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; CHECK-NEXT: s_cmp_lg_u32 s4, 0
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; CHECK-NEXT: s_cselect_b32 s4, 1, 0
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; CHECK-NEXT: s_and_b32 s4, s4, 1
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; CHECK-NEXT: s_cmp_lg_u32 s4, 0
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; CHECK-NEXT: s_cbranch_scc0 BB4_5
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; CHECK-NEXT: BB4_4: ; %bb12
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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; CHECK-NEXT: BB4_5: ; %bb11
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; CHECK-NEXT: v_mov_b32_e32 v0, 4.0
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; CHECK-NEXT: buffer_store_dword v0, v0, s[0:3], 0 offen
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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bb:
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%tmp = load i32, i32 addrspace(4)* @external_constant
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%ptr = load float*, float* addrspace(4)* @const.ptr
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%tmp1 = icmp ne i32 %tmp, 0
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br i1 %tmp1, label %bb12, label %bb2
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bb2:
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%tmp4 = load float, float* %ptr, align 4
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%tmp5 = fcmp olt float %tmp4, 1.0
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%tmp6 = or i1 %tmp5, false
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br i1 %tmp6, label %bb8, label %bb7
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bb7:
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br label %bb8
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bb8:
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%tmp9 = phi i32 [ 0, %bb7 ], [ -1, %bb2 ]
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%tmp10 = icmp eq i32 %tmp9, 0
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br i1 %tmp10, label %bb11, label %bb12
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bb11:
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store float 4.0, float addrspace(5)* undef, align 4
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br label %bb12
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bb12:
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ret void
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}
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define amdgpu_kernel void @break_loop(i32 %arg) {
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; CHECK-LABEL: break_loop:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_load_dword s2, s[4:5], 0x0
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; CHECK-NEXT: s_mov_b64 s[0:1], 0
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; CHECK-NEXT: ; implicit-def: $vgpr1
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_subrev_u32_e32 v0, s2, v0
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; CHECK-NEXT: s_branch BB5_2
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; CHECK-NEXT: BB5_1: ; %Flow
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; CHECK-NEXT: ; in Loop: Header=BB5_2 Depth=1
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; CHECK-NEXT: s_and_b64 s[2:3], exec, s[2:3]
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; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
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; CHECK-NEXT: s_andn2_b64 exec, exec, s[0:1]
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; CHECK-NEXT: s_cbranch_execz BB5_4
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; CHECK-NEXT: BB5_2: ; %bb1
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: v_add_u32_e32 v1, 1, v1
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; CHECK-NEXT: v_cmp_le_i32_e32 vcc, 0, v1
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; CHECK-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, 1
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; CHECK-NEXT: s_cbranch_vccnz BB5_1
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; CHECK-NEXT: ; %bb.3: ; %bb4
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; CHECK-NEXT: ; in Loop: Header=BB5_2 Depth=1
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; CHECK-NEXT: global_load_dword v2, v[0:1], off
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_cmp_ge_i32_e64 s[2:3], v0, v2
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; CHECK-NEXT: s_branch BB5_1
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; CHECK-NEXT: BB5_4: ; %bb9
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; CHECK-NEXT: s_endpgm
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bb:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp = sub i32 %id, %arg
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br label %bb1
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bb1:
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%lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %bb4 ]
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%lsr.iv.next = add i32 %lsr.iv, 1
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%cmp0 = icmp slt i32 %lsr.iv.next, 0
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br i1 %cmp0, label %bb4, label %bb9
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bb4:
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%load = load volatile i32, i32 addrspace(1)* undef, align 4
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%cmp1 = icmp slt i32 %tmp, %load
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br i1 %cmp1, label %bb1, label %bb9
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bb9:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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