You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
147 lines
5.2 KiB
147 lines
5.2 KiB
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
|
|
# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
|
|
|
|
---
|
|
name: readlane_ss
|
|
legalized: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0, $sgpr1
|
|
; CHECK-LABEL: name: readlane_ss
|
|
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
|
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
|
|
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
|
; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[COPY1]](s32)
|
|
%0:_(s32) = COPY $sgpr0
|
|
%1:_(s32) = COPY $sgpr1
|
|
%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
|
|
...
|
|
|
|
---
|
|
name: readlane_vs
|
|
legalized: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0, $sgpr0
|
|
; CHECK-LABEL: name: readlane_vs
|
|
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
|
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
|
; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY]](s32), [[COPY1]](s32)
|
|
%0:_(s32) = COPY $vgpr0
|
|
%1:_(s32) = COPY $sgpr0
|
|
%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
|
|
...
|
|
|
|
---
|
|
name: readlane_vv
|
|
legalized: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0, $vgpr1
|
|
; CHECK-LABEL: name: readlane_vv
|
|
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
|
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
|
|
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
|
|
; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY]](s32), [[V_READFIRSTLANE_B32_]](s32)
|
|
%0:_(s32) = COPY $vgpr0
|
|
%1:_(s32) = COPY $vgpr1
|
|
%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
|
|
...
|
|
|
|
---
|
|
name: readlane_sv
|
|
legalized: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0, $sgpr0
|
|
; CHECK-LABEL: name: readlane_sv
|
|
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
|
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
|
|
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
|
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
|
|
; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[V_READFIRSTLANE_B32_]](s32)
|
|
%0:_(s32) = COPY $sgpr0
|
|
%1:_(s32) = COPY $vgpr0
|
|
%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
|
|
...
|
|
|
|
---
|
|
name: readlane_aa
|
|
legalized: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $agpr0, $agpr1
|
|
; CHECK-LABEL: name: readlane_aa
|
|
; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
|
|
; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
|
|
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
|
; CHECK: [[COPY3:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s32)
|
|
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY3]](s32), implicit $exec
|
|
; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[V_READFIRSTLANE_B32_]](s32)
|
|
; CHECK: S_ENDPGM 0, implicit [[INT]](s32)
|
|
%0:_(s32) = COPY $agpr0
|
|
%1:_(s32) = COPY $agpr1
|
|
%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
|
|
S_ENDPGM 0, implicit %2
|
|
...
|
|
|
|
---
|
|
name: readlane_as
|
|
legalized: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $agpr0, $sgpr0
|
|
; CHECK-LABEL: name: readlane_as
|
|
; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
|
|
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
|
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
|
; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[COPY1]](s32)
|
|
%0:_(s32) = COPY $agpr0
|
|
%1:_(s32) = COPY $sgpr0
|
|
%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
|
|
...
|
|
|
|
---
|
|
name: readlane_sa
|
|
legalized: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $agpr0, $sgpr0
|
|
; CHECK-LABEL: name: readlane_sa
|
|
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
|
; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
|
|
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
|
|
; CHECK: [[COPY3:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s32)
|
|
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY3]](s32), implicit $exec
|
|
; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY2]](s32), [[V_READFIRSTLANE_B32_]](s32)
|
|
%0:_(s32) = COPY $sgpr0
|
|
%1:_(s32) = COPY $agpr0
|
|
%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
|
|
...
|
|
|
|
---
|
|
name: readlane_va
|
|
legalized: true
|
|
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0, $agpr0
|
|
; CHECK-LABEL: name: readlane_va
|
|
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
|
; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
|
|
; CHECK: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY [[COPY1]](s32)
|
|
; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY2]](s32), implicit $exec
|
|
; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), [[COPY]](s32), [[V_READFIRSTLANE_B32_]](s32)
|
|
%0:_(s32) = COPY $vgpr0
|
|
%1:_(s32) = COPY $agpr0
|
|
%2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readlane), %0, %1
|
|
...
|