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257 lines
8.2 KiB
257 lines
8.2 KiB
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
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; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
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; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
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; ===================================================================================
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; V_ADD3_U32
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; ===================================================================================
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define amdgpu_ps float @add3(i32 %a, i32 %b, i32 %c) {
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; VI-LABEL: add3:
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; VI: ; %bb.0:
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; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: add3:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_add3_u32 v0, v0, v1, v2
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: add3:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_add3_u32 v0, v0, v1, v2
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; GFX10-NEXT: ; return to shader part epilog
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%x = add i32 %a, %b
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%result = add i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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; V_MAD_U32_U24 is given higher priority.
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define amdgpu_ps float @mad_no_add3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
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; VI-LABEL: mad_no_add3:
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; VI: ; %bb.0:
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; VI-NEXT: v_mad_u32_u24 v0, v0, v1, v4
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; VI-NEXT: v_mad_u32_u24 v0, v2, v3, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: mad_no_add3:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mad_u32_u24 v0, v0, v1, v4
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; GFX9-NEXT: v_mad_u32_u24 v0, v2, v3, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: mad_no_add3:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_mad_u32_u24 v0, v0, v1, v4
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; GFX10-NEXT: v_mad_u32_u24 v0, v2, v3, v0
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; GFX10-NEXT: ; return to shader part epilog
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%a0 = shl i32 %a, 8
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%a1 = lshr i32 %a0, 8
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%b0 = shl i32 %b, 8
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%b1 = lshr i32 %b0, 8
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%mul1 = mul i32 %a1, %b1
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%c0 = shl i32 %c, 8
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%c1 = lshr i32 %c0, 8
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%d0 = shl i32 %d, 8
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%d1 = lshr i32 %d0, 8
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%mul2 = mul i32 %c1, %d1
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%add0 = add i32 %e, %mul1
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%add1 = add i32 %mul2, %add0
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%bc = bitcast i32 %add1 to float
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ret float %bc
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}
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; ThreeOp instruction variant not used due to Constant Bus Limitations
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; TODO: with reassociation it is possible to replace a v_add_u32_e32 with a s_add_i32
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define amdgpu_ps float @add3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
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; VI-LABEL: add3_vgpr_b:
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; VI: ; %bb.0:
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; VI-NEXT: s_add_i32 s3, s3, s2
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; VI-NEXT: v_add_u32_e32 v0, vcc, s3, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: add3_vgpr_b:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_add_i32 s3, s3, s2
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; GFX9-NEXT: v_add_u32_e32 v0, s3, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: add3_vgpr_b:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_add3_u32 v0, s3, s2, v0
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; GFX10-NEXT: ; return to shader part epilog
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%x = add i32 %a, %b
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%result = add i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @add3_vgpr_all2(i32 %a, i32 %b, i32 %c) {
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; VI-LABEL: add3_vgpr_all2:
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; VI: ; %bb.0:
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; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2
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; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: add3_vgpr_all2:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_add3_u32 v0, v1, v2, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: add3_vgpr_all2:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_add3_u32 v0, v1, v2, v0
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; GFX10-NEXT: ; return to shader part epilog
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%x = add i32 %b, %c
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%result = add i32 %a, %x
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @add3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {
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; VI-LABEL: add3_vgpr_bc:
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; VI: ; %bb.0:
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; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
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; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: add3_vgpr_bc:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_add3_u32 v0, s2, v0, v1
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: add3_vgpr_bc:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_add3_u32 v0, s2, v0, v1
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; GFX10-NEXT: ; return to shader part epilog
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%x = add i32 %a, %b
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%result = add i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @add3_vgpr_const(i32 %a, i32 %b) {
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; VI-LABEL: add3_vgpr_const:
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; VI: ; %bb.0:
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; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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; VI-NEXT: v_add_u32_e32 v0, vcc, 16, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: add3_vgpr_const:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_add3_u32 v0, v0, v1, 16
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: add3_vgpr_const:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_add3_u32 v0, v0, v1, 16
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; GFX10-NEXT: ; return to shader part epilog
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%x = add i32 %a, %b
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%result = add i32 %x, 16
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x) {
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; VI-LABEL: add3_multiuse_outer:
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; VI: ; %bb.0:
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; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
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; VI-NEXT: v_mul_lo_u32 v1, v0, v3
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: add3_multiuse_outer:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_add3_u32 v0, v0, v1, v2
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; GFX9-NEXT: v_mul_lo_u32 v1, v0, v3
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: add3_multiuse_outer:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_add3_u32 v0, v0, v1, v2
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; GFX10-NEXT: v_mul_lo_u32 v1, v0, v3
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; GFX10-NEXT: ; return to shader part epilog
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%inner = add i32 %a, %b
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%outer = add i32 %inner, %c
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%x1 = mul i32 %outer, %x
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%r1 = insertelement <2 x i32> undef, i32 %outer, i32 0
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%r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1
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%bc = bitcast <2 x i32> %r0 to <2 x float>
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ret <2 x float> %bc
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}
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define amdgpu_ps <2 x float> @add3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
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; VI-LABEL: add3_multiuse_inner:
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; VI: ; %bb.0:
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; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1
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; VI-NEXT: v_add_u32_e32 v1, vcc, v0, v2
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: add3_multiuse_inner:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
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; GFX9-NEXT: v_add_u32_e32 v1, v0, v2
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: add3_multiuse_inner:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
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; GFX10-NEXT: v_add_nc_u32_e32 v1, v0, v2
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; GFX10-NEXT: ; return to shader part epilog
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%inner = add i32 %a, %b
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%outer = add i32 %inner, %c
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%r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
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%r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1
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%bc = bitcast <2 x i32> %r0 to <2 x float>
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ret <2 x float> %bc
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}
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; A case where uniform values end up in VGPRs -- we could use v_add3_u32 here,
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; but we don't.
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define amdgpu_ps float @add3_uniform_vgpr(float inreg %a, float inreg %b, float inreg %c) {
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; VI-LABEL: add3_uniform_vgpr:
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; VI: ; %bb.0:
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; VI-NEXT: v_mov_b32_e32 v2, 0x40400000
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; VI-NEXT: v_add_f32_e64 v0, s2, 1.0
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; VI-NEXT: v_add_f32_e64 v1, s3, 2.0
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; VI-NEXT: v_add_f32_e32 v2, s4, v2
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; VI-NEXT: v_add_u32_e32 v0, vcc, v1, v0
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; VI-NEXT: v_add_u32_e32 v0, vcc, v2, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: add3_uniform_vgpr:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v2, 0x40400000
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; GFX9-NEXT: v_add_f32_e64 v0, s2, 1.0
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; GFX9-NEXT: v_add_f32_e64 v1, s3, 2.0
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; GFX9-NEXT: v_add_f32_e32 v2, s4, v2
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; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
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; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: add3_uniform_vgpr:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_add_f32_e64 v0, s2, 1.0
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; GFX10-NEXT: v_add_f32_e64 v1, s3, 2.0
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; GFX10-NEXT: v_add_f32_e64 v2, 0x40400000, s4
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; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
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; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
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; GFX10-NEXT: ; return to shader part epilog
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%a1 = fadd float %a, 1.0
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%b2 = fadd float %b, 2.0
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%c3 = fadd float %c, 3.0
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%bc.a = bitcast float %a1 to i32
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%bc.b = bitcast float %b2 to i32
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%bc.c = bitcast float %c3 to i32
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%x = add i32 %bc.a, %bc.b
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%result = add i32 %x, %bc.c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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