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367 lines
13 KiB
367 lines
13 KiB
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
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; GCN-LABEL: {{^}}add1:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_addc_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, 0, v{{[0-9]+}}, [[CC]]
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; GCN-NOT: v_cndmask
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; GFX9-LABEL: {{^}}add1:
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; GFX9: v_addc_co_u32_e{{32|64}} v{{[0-9]+}}, vcc
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define amdgpu_kernel void @add1(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp = icmp ugt i32 %x, %y
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%ext = zext i1 %cmp to i32
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%add = add i32 %v, %ext
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store i32 %add, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}add1_i16:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_addc_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, 0, v{{[0-9]+}}, [[CC]]
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; GCN-NOT: v_cndmask
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; GFX9-LABEL: {{^}}add1_i16:
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; GFX9: v_addc_co_u32_e{{32|64}} v{{[0-9]+}}, vcc
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define i16 @add1_i16(i32 addrspace(1)* nocapture %arg, i16 addrspace(1)* nocapture %dst) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp = icmp ugt i32 %x, %y
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%ext = zext i1 %cmp to i32
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%add = add i32 %v, %ext
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%trunc = trunc i32 %add to i16
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ret i16 %trunc
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}
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; GCN-LABEL: {{^}}sub1:
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; GCN: v_cmp_gt_u32_e32 vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
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; GCN-NOT: v_cndmask
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; GFX9-LABEL: {{^}}sub1:
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; GFX9: v_subbrev_co_u32_e{{32|64}} v{{[0-9]+}}, vcc
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define amdgpu_kernel void @sub1(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%add = add i32 %v, %ext
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store i32 %add, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}add_adde:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_addc_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CC]]
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; GCN-NOT: v_cndmask
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; GCN-NOT: v_add
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; GFX9-LABEL: {{^}}add_adde:
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; GFX9: v_addc_co_u32_e{{32|64}} v{{[0-9]+}}, vcc
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define amdgpu_kernel void @add_adde(i32 addrspace(1)* nocapture %arg, i32 %a) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp = icmp ugt i32 %x, %y
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%ext = zext i1 %cmp to i32
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%adde = add i32 %v, %ext
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%add2 = add i32 %adde, %a
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store i32 %add2, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}adde_add:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_addc_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CC]]
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; GCN-NOT: v_cndmask
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; GCN-NOT: v_add
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; GFX9-LABEL: {{^}}adde_add:
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; GFX9: v_addc_co_u32_e{{32|64}} v{{[0-9]+}}, vcc
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define amdgpu_kernel void @adde_add(i32 addrspace(1)* nocapture %arg, i32 %a) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp = icmp ugt i32 %x, %y
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%ext = zext i1 %cmp to i32
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%add = add i32 %v, %a
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%adde = add i32 %add, %ext
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store i32 %adde, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}sub_sube:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_subb_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CC]]
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; GCN-NOT: v_cndmask
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; GCN-NOT: v_sub
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; GFX9-LABEL: {{^}}sub_sube:
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; GFX9: v_subb_co_u32_e{{32|64}} v{{[0-9]+}}, vcc
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define amdgpu_kernel void @sub_sube(i32 addrspace(1)* nocapture %arg, i32 %a) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%adde = add i32 %v, %ext
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%sub = sub i32 %adde, %a
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store i32 %sub, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}sub_sube_commuted:
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; GCN-DAG: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-DAG: buffer_load_dword [[V:v[0-9]+]],
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; GCN: v_cndmask_b32_e64 [[CCZEXT:v[0-9]+]], 0, 1, [[CC]]
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; GCN: v_sub_i32_e32 [[SUB:v[0-9]+]], vcc, [[CCZEXT]], v4
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; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, {{.*}}, [[SUB]]
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; GCN: v_add_i32_e32 {{.*}}, 0x64, [[ADD]]
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; GFX9-LABEL: {{^}}sub_sube_commuted:
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; GFX9-DAG: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GFX9-DAG: global_load_dword [[V:v[0-9]+]],
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; GFX9-DAG: v_cndmask_b32_e64 [[CCZEXT:v[0-9]+]], 0, 1, [[CC]]
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; GFX9: v_sub_u32_e32 {{.*}}, [[CCZEXT]]
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; GFX9: v_add_u32_e32
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; GFX9: v_add_u32_e32 {{.*}}, 0x64,
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define amdgpu_kernel void @sub_sube_commuted(i32 addrspace(1)* nocapture %arg, i32 %a) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%adde = add i32 %v, %ext
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%sub = sub i32 %adde, %a
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%sub2 = sub i32 100, %sub
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store i32 %sub2, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}sube_sub:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_subb_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CC]]
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; GCN-NOT: v_cndmask
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; GCN-NOT: v_sub
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; GFX9-LABEL: {{^}}sube_sub:
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; GFX9: v_subb_co_u32_e{{32|64}} v{{[0-9]+}}, vcc
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define amdgpu_kernel void @sube_sub(i32 addrspace(1)* nocapture %arg, i32 %a) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%sub = sub i32 %v, %a
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%adde = add i32 %sub, %ext
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store i32 %adde, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}zext_flclass:
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; GCN: v_cmp_class_f32_e{{32|64}} [[CC:[^,]+]],
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; GCN: v_addc_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, 0, v{{[0-9]+}}, [[CC]]
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; GCN-NOT: v_cndmask
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; GFX9-LABEL: {{^}}zext_flclass:
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; GFX9: v_addc_co_u32_e{{32|64}} v{{[0-9]+}}, vcc
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define amdgpu_kernel void @zext_flclass(i32 addrspace(1)* nocapture %arg, float %x) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp = tail call zeroext i1 @llvm.amdgcn.class.f32(float %x, i32 608)
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%ext = zext i1 %cmp to i32
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%add = add i32 %v, %ext
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store i32 %add, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}sext_flclass:
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; GCN: v_cmp_class_f32_e32 vcc,
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; GCN: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
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; GCN-NOT: v_cndmask
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; GFX9-LABEL: {{^}}sext_flclass:
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; GFX9: v_subbrev_co_u32_e32 v{{[0-9]+}}, vcc
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define amdgpu_kernel void @sext_flclass(i32 addrspace(1)* nocapture %arg, float %x) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp = tail call zeroext i1 @llvm.amdgcn.class.f32(float %x, i32 608)
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%ext = sext i1 %cmp to i32
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%add = add i32 %v, %ext
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store i32 %add, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}add_and:
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; GCN: s_and_b64 [[CC:[^,]+]],
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; GCN: v_addc_u32_e{{32|64}} v{{[0-9]+}}, {{[^,]+}}, 0, v{{[0-9]+}}, [[CC]]
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; GCN-NOT: v_cndmask
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; GFX9-LABEL: {{^}}add_and:
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; GFX9: v_addc_co_u32_e{{32|64}} v{{[0-9]+}}, vcc
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define amdgpu_kernel void @add_and(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp1 = icmp ugt i32 %x, %y
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%cmp2 = icmp ugt i32 %x, 1
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%cmp = and i1 %cmp1, %cmp2
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%ext = zext i1 %cmp to i32
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%add = add i32 %v, %ext
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store i32 %add, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; sub x, sext (setcc) => addcarry x, 0, setcc
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; GCN-LABEL: {{^}}cmp_sub_sext:
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; GCN: v_cmp_gt_u32_e32 vcc, v
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; GCN-NOT: vcc
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; GCN: v_addc_u32_e32 [[RESULT:v[0-9]+]], vcc, 0, v{{[0-9]+}}, vcc
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define amdgpu_kernel void @cmp_sub_sext(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%add = sub i32 %v, %ext
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store i32 %add, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; sub x, zext (setcc) => subcarry x, 0, setcc
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; GCN-LABEL: {{^}}cmp_sub_zext:
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; GCN: v_cmp_gt_u32_e32 vcc, v
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; GCN-NOT: vcc
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; GCN: v_subbrev_u32_e32 [[RESULT:v[0-9]+]], vcc, 0, v{{[0-9]+}}, vcc
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define amdgpu_kernel void @cmp_sub_zext(i32 addrspace(1)* nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp = icmp ugt i32 %x, %y
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%ext = zext i1 %cmp to i32
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%add = sub i32 %v, %ext
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store i32 %add, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}sub_addcarry:
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; GCN: v_cmp_gt_u32_e32 vcc, v
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; GCN-NOT: vcc
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; GCN: v_addc_u32_e32 [[ADDC:v[0-9]+]], vcc, 0, v{{[0-9]+}}, vcc
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; GCN-NOT: vcc
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; GCN: v_subrev_i32_e32 [[RESULT:v[0-9]+]], vcc,
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define amdgpu_kernel void @sub_addcarry(i32 addrspace(1)* nocapture %arg, i32 %a) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp = icmp ugt i32 %x, %y
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%ext = zext i1 %cmp to i32
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%adde = add i32 %v, %ext
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%add2 = sub i32 %adde, %a
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store i32 %add2, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}sub_subcarry:
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; GCN: v_cmp_gt_u32_e32 vcc, v
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; GCN-NOT: vcc
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; GCN: v_subb_u32_e32 [[RESULT:v[0-9]+]], vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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define amdgpu_kernel void @sub_subcarry(i32 addrspace(1)* nocapture %arg, i32 %a) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp = icmp ugt i32 %x, %y
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%ext = zext i1 %cmp to i32
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%adde = sub i32 %v, %ext
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%add2 = sub i32 %adde, %a
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store i32 %add2, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; Check case where sub is commuted with zext
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; GCN-LABEL: {{^}}sub_zext_setcc_commute:
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; GCN: v_cmp_gt_u32_e32 vcc, v
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; GCN: v_cndmask
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; GCN: v_sub_i32_e32
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; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc,
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; GCN: v_subrev_i32_e32 [[RESULT:v[0-9]+]], vcc, s{{[0-9]+}}, [[ADD]]
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define amdgpu_kernel void @sub_zext_setcc_commute(i32 addrspace(1)* nocapture %arg, i32 %a, i32%b) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
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%v = load i32, i32 addrspace(1)* %gep, align 4
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%cmp = icmp ugt i32 %x, %y
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%ext = zext i1 %cmp to i32
|
|
%adde = sub i32 %v, %ext
|
|
%sub = sub i32 %a, %adde
|
|
%sub2 = sub i32 %sub, %b
|
|
store i32 %sub2, i32 addrspace(1)* %gep, align 4
|
|
ret void
|
|
}
|
|
|
|
; Check case where sub is commuted with sext
|
|
; GCN-LABEL: {{^}}sub_sext_setcc_commute:
|
|
; GCN: v_cmp_gt_u32_e32 vcc, v
|
|
; GCN: v_cndmask
|
|
; GCN: v_sub_i32_e32
|
|
; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc,
|
|
; GCN: v_subrev_i32_e32 [[RESULT:v[0-9]+]], vcc, s{{[0-9]+}}, [[ADD]]
|
|
define amdgpu_kernel void @sub_sext_setcc_commute(i32 addrspace(1)* nocapture %arg, i32 %a, i32%b) {
|
|
bb:
|
|
%x = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
%y = tail call i32 @llvm.amdgcn.workitem.id.y()
|
|
%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %x
|
|
%v = load i32, i32 addrspace(1)* %gep, align 4
|
|
%cmp = icmp ugt i32 %x, %y
|
|
%ext = sext i1 %cmp to i32
|
|
%adde = sub i32 %v, %ext
|
|
%sub = sub i32 %a, %adde
|
|
%sub2 = sub i32 %sub, %b
|
|
store i32 %sub2, i32 addrspace(1)* %gep, align 4
|
|
ret void
|
|
}
|
|
|
|
declare i1 @llvm.amdgcn.class.f32(float, i32) #0
|
|
|
|
declare i32 @llvm.amdgcn.workitem.id.x() #0
|
|
|
|
declare i32 @llvm.amdgcn.workitem.id.y() #0
|
|
|
|
attributes #0 = { nounwind readnone speculatable }
|