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152 lines
6.0 KiB
152 lines
6.0 KiB
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,NOTGFX9,GCN-SDAG %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CIPLUS,NOTGFX9,CIPLUS-SDAG,GCN-SDAG %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CIPLUS,NOTGFX9,CIPLUS-SDAG,GCN-SDAG %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CIPLUS,GFX9,CIPLUS-SDAG,GCN-SDAG %s
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; GCN-LABEL: {{^}}ds_append_lds:
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; GCN: s_load_dword [[PTR:s[0-9]+]]
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; GCN: s_mov_b32 m0, [[PTR]]
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; GCN: ds_append [[RESULT:v[0-9]+]]{{$}}
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; GCN-NOT: buffer_wbinvl1
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; GCN: {{.*}}store{{.*}} [[RESULT]]
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define amdgpu_kernel void @ds_append_lds(i32 addrspace(3)* %lds, i32 addrspace(1)* %out) #0 {
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%val = call i32 @llvm.amdgcn.ds.append.p3i32(i32 addrspace(3)* %lds, i1 false)
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}ds_append_lds_max_offset:
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; GCN: s_load_dword [[PTR:s[0-9]+]]
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; GCN: s_mov_b32 m0, [[PTR]]
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; GCN: ds_append [[RESULT:v[0-9]+]] offset:65532{{$}}
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; GCN-NOT: buffer_wbinvl1
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; GCN: {{.*}}store{{.*}} [[RESULT]]
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define amdgpu_kernel void @ds_append_lds_max_offset(i32 addrspace(3)* %lds, i32 addrspace(1)* %out) #0 {
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%gep = getelementptr inbounds i32, i32 addrspace(3)* %lds, i32 16383
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%val = call i32 @llvm.amdgcn.ds.append.p3i32(i32 addrspace(3)* %gep, i1 false)
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}ds_append_no_fold_offset_si:
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; GCN: s_load_dword [[PTR:s[0-9]+]]
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; SI: s_add_i32 [[PTR]], [[PTR]], 16
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; SI: s_mov_b32 m0, [[PTR]]
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; SI: ds_append [[RESULT:v[0-9]+]]{{$}}
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; CIPLUS: s_mov_b32 m0, [[PTR]]
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; CIPLUS: ds_append [[RESULT:v[0-9]+]] offset:16{{$}}
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; GCN-NOT: buffer_wbinvl1
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; GCN: {{.*}}store{{.*}} [[RESULT]]
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define amdgpu_kernel void @ds_append_no_fold_offset_si(i32 addrspace(3)* addrspace(4)* %lds.ptr, i32 addrspace(1)* %out) #0 {
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%lds = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(4)* %lds.ptr, align 4
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%gep = getelementptr inbounds i32, i32 addrspace(3)* %lds, i32 4
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%val = call i32 @llvm.amdgcn.ds.append.p3i32(i32 addrspace(3)* %gep, i1 false)
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}ds_append_lds_over_max_offset:
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; GCN: s_load_dword [[PTR:s[0-9]+]]
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; SI-SDAG: s_bitset1_b32 [[PTR]], 16
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; CIPLUS-SDAG: s_add_i32 [[PTR]], [[PTR]], 0x10000
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; GCN-SDAG: s_mov_b32 m0, [[PTR]]
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; SI-GISEL: s_bitset1_b32 m0, 16
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; CIPLUS-GISEL: s_add_u32 m0, [[PTR]], 0x10000
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; GCN: ds_append [[RESULT:v[0-9]+]]{{$}}
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; GCN-NOT: buffer_wbinvl1
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; GCN: {{.*}}store{{.*}} [[RESULT]]
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define amdgpu_kernel void @ds_append_lds_over_max_offset(i32 addrspace(3)* %lds, i32 addrspace(1)* %out) #0 {
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%gep = getelementptr inbounds i32, i32 addrspace(3)* %lds, i32 16384
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%val = call i32 @llvm.amdgcn.ds.append.p3i32(i32 addrspace(3)* %gep, i1 false)
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}ds_append_lds_vgpr_addr:
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; GCN-SDAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v0
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; GCN-SDAG: s_mov_b32 m0, [[READLANE]]
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; GCN-GISEL: v_readfirstlane_b32 m0, v0
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; GCN: ds_append [[RESULT:v[0-9]+]]{{$}}
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; GCN-NOT: buffer_wbinvl1
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; GCN: {{.*}}store{{.*}} [[RESULT]]
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define void @ds_append_lds_vgpr_addr(i32 addrspace(3)* %lds, i32 addrspace(1)* %out) #0 {
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%val = call i32 @llvm.amdgcn.ds.append.p3i32(i32 addrspace(3)* %lds, i1 false)
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}ds_append_gds:
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; GCN: s_load_dword [[PTR:s[0-9]+]]
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; GCN: s_mov_b32 m0, [[PTR]]
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; GCN: ds_append [[RESULT:v[0-9]+]] gds{{$}}
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; GCN-NOT: buffer_wbinvl1
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; GCN: {{.*}}store{{.*}} [[RESULT]]
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define amdgpu_kernel void @ds_append_gds(i32 addrspace(2)* %gds, i32 addrspace(1)* %out) #0 {
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%val = call i32 @llvm.amdgcn.ds.append.p2i32(i32 addrspace(2)* %gds, i1 false)
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}ds_append_gds_max_offset:
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; GCN: s_load_dword [[PTR:s[0-9]+]]
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; GCN: s_mov_b32 m0, [[PTR]]
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; GCN: ds_append [[RESULT:v[0-9]+]] offset:65532 gds{{$}}
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; GCN-NOT: buffer_wbinvl1
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; GCN: {{.*}}store{{.*}} [[RESULT]]
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define amdgpu_kernel void @ds_append_gds_max_offset(i32 addrspace(2)* %gds, i32 addrspace(1)* %out) #0 {
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%gep = getelementptr inbounds i32, i32 addrspace(2)* %gds, i32 16383
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%val = call i32 @llvm.amdgcn.ds.append.p2i32(i32 addrspace(2)* %gep, i1 false)
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}ds_append_gds_over_max_offset:
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; GCN-NOT: buffer_wbinvl1
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define amdgpu_kernel void @ds_append_gds_over_max_offset(i32 addrspace(2)* %gds, i32 addrspace(1)* %out) #0 {
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%gep = getelementptr inbounds i32, i32 addrspace(2)* %gds, i32 16384
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%val = call i32 @llvm.amdgcn.ds.append.p2i32(i32 addrspace(2)* %gep, i1 false)
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}ds_append_lds_m0_restore:
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; GCN: s_load_dword [[PTR:s[0-9]+]]
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; GCN: s_mov_b32 m0, [[PTR]]
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; GCN: ds_append [[RESULT:v[0-9]+]]{{$}}
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; GCN-NOT: buffer_wbinvl1
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; NOTGFX9: s_mov_b32 m0, -1
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; GFX9-NOT: m0
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; GCN: _store_dword
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; GCN: ds_read_b32
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define amdgpu_kernel void @ds_append_lds_m0_restore(i32 addrspace(3)* %lds, i32 addrspace(1)* %out) #0 {
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%val0 = call i32 @llvm.amdgcn.ds.append.p3i32(i32 addrspace(3)* %lds, i1 false)
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store i32 %val0, i32 addrspace(1)* %out
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%val1 = load volatile i32, i32 addrspace(3)* %lds
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ret void
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}
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; Make sure this selects successfully with no use. The result register needs to be constrained.
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; GCN-LABEL: {{^}}ds_append_lds_no_use:
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; GCN: s_load_dword [[PTR:s[0-9]+]]
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; GCN: s_mov_b32 m0, [[PTR]]
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; GCN: ds_append [[RESULT:v[0-9]+]] offset:65532{{$}}
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define amdgpu_kernel void @ds_append_lds_no_use(i32 addrspace(3)* %lds, i32 addrspace(1)* %out) #0 {
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%gep = getelementptr inbounds i32, i32 addrspace(3)* %lds, i32 16383
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%val = call i32 @llvm.amdgcn.ds.append.p3i32(i32 addrspace(3)* %gep, i1 false)
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ret void
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}
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declare i32 @llvm.amdgcn.ds.append.p3i32(i32 addrspace(3)* nocapture, i1 immarg) #1
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declare i32 @llvm.amdgcn.ds.append.p2i32(i32 addrspace(2)* nocapture, i1 immarg) #1
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attributes #0 = { nounwind }
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attributes #1 = { argmemonly convergent nounwind }
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