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88 lines
3.8 KiB
88 lines
3.8 KiB
; RUN: llc -march=amdgcn < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GFX8 -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=CM -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}test:
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; EG: LOG_IEEE
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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; GCN: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0x3e9a209a, v{{[0-9]+}}
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define void @test(float addrspace(1)* %out, float %in) {
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entry:
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%res = call float @llvm.log10.f32(float %in)
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store float %res, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}testv2:
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; EG: LOG_IEEE
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; EG: LOG_IEEE
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; FIXME: We should be able to merge these packets together on Cayman so we
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; have a maximum of 4 instructions.
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-DAG: s_mov_b32 [[R_F32_LOG_CONST:s[0-9]+]], 0x3e9a209a
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; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
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define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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entry:
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%res = call <2 x float> @llvm.log10.v2f32(<2 x float> %in)
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store <2 x float> %res, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}testv4:
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; EG: LOG_IEEE
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; EG: LOG_IEEE
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; EG: LOG_IEEE
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; EG: LOG_IEEE
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; FIXME: We should be able to merge these packets together on Cayman so we
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; have a maximum of 4 instructions.
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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; CM-DAG: LOG_IEEE T{{[0-9]+\.[XYZW]}}
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; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-DAG: s_mov_b32 [[R_F32_LOG_CONST:s[0-9]+]], 0x3e9a209a
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; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-DAG: v_log_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, [[R_F32_LOG_CONST]], v{{[0-9]+}}
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define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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entry:
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%res = call <4 x float> @llvm.log10.v4f32(<4 x float> %in)
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store <4 x float> %res, <4 x float> addrspace(1)* %out
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ret void
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}
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declare float @llvm.log10.f32(float) readnone
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declare <2 x float> @llvm.log10.v2f32(<2 x float>) readnone
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declare <4 x float> @llvm.log10.v4f32(<4 x float>) readnone
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