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221 lines
11 KiB
221 lines
11 KiB
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck %s
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# Check that SILoadStoreOptimizer honors memory dependencies between moved
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# instructions.
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#
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# The following IR snippet would usually be optimized by the peephole optimizer.
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# However, an equivalent situation can occur with buffer instructions as well.
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# CHECK-LABEL: name: mem_dependency
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# CHECK: DS_READ2_B32 %0, 0, 1,
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# CHECK: DS_WRITE_B32 %0, killed %1, 64,
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# CHECK: DS_READ2_B32 %0, 16, 17,
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# CHECK: DS_WRITE_B32 killed %0, %5, 0
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--- |
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define amdgpu_kernel void @mem_dependency(i32 addrspace(3)* %ptr.0) nounwind {
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%ptr.4 = getelementptr i32, i32 addrspace(3)* %ptr.0, i32 1
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%ptr.64 = getelementptr i32, i32 addrspace(3)* %ptr.0, i32 16
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%1 = load i32, i32 addrspace(3)* %ptr.0
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store i32 %1, i32 addrspace(3)* %ptr.64
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%2 = load i32, i32 addrspace(3)* %ptr.64
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%3 = load i32, i32 addrspace(3)* %ptr.4
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%4 = add i32 %2, %3
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store i32 %4, i32 addrspace(3)* %ptr.0
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ret void
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}
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@lds0 = external dso_local unnamed_addr addrspace(3) global [256 x i32], align 4
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@lds1 = external dso_local unnamed_addr addrspace(3) global [256 x i32], align 4
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@lds2 = external dso_local unnamed_addr addrspace(3) global [256 x i32], align 4
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@lds3 = external dso_local unnamed_addr addrspace(3) global [256 x i32], align 4
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define void @asm_defines_address() #0 {
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bb:
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%tmp1 = load i32, i32 addrspace(3)* getelementptr inbounds ([256 x i32], [256 x i32] addrspace(3)* @lds0, i32 0, i32 0), align 4
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%0 = and i32 %tmp1, 255
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%tmp3 = load i32, i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds1, i32 0, i32 undef), align 4
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%tmp6 = load i32, i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds3, i32 0, i32 undef), align 4
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%tmp7 = tail call i32 asm "v_or_b32 $0, 0, $1", "=v,v"(i32 %tmp6) #1
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%tmp10 = lshr i32 %tmp7, 16
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%tmp11 = and i32 %tmp10, 255
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%tmp12 = getelementptr inbounds [256 x i32], [256 x i32] addrspace(3)* @lds1, i32 0, i32 %tmp11
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%tmp13 = load i32, i32 addrspace(3)* %tmp12, align 4
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%tmp14 = xor i32 %tmp3, %tmp13
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%tmp15 = lshr i32 %tmp14, 8
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%tmp16 = and i32 %tmp15, 16711680
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%tmp19 = lshr i32 %tmp16, 16
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%tmp20 = and i32 %tmp19, 255
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%tmp21 = getelementptr inbounds [256 x i32], [256 x i32] addrspace(3)* @lds1, i32 0, i32 %tmp20
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%tmp22 = load i32, i32 addrspace(3)* %tmp21, align 4
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%tmp24 = load i32, i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds2, i32 0, i32 undef), align 4
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%tmp25 = xor i32 %tmp22, %tmp24
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%tmp26 = and i32 %tmp25, -16777216
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%tmp28 = or i32 %0, %tmp26
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store volatile i32 %tmp28, i32 addrspace(1)* undef
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ret void
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}
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attributes #0 = { convergent nounwind }
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attributes #1 = { convergent nounwind readnone }
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define amdgpu_kernel void @move_waw_hazards() #0 {
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ret void
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}
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attributes #0 = { convergent nounwind }
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define amdgpu_kernel void @merge_mmos(i32 addrspace(1)* %ptr_addr1) { ret void }
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define amdgpu_kernel void @reorder_offsets(i32 addrspace(1)* %reorder_addr1) { ret void }
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...
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---
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name: mem_dependency
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0:
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liveins: $vgpr0
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%1:vgpr_32 = COPY $vgpr0
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$m0 = S_MOV_B32 -1
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%2:vgpr_32 = DS_READ_B32 %1, 0, 0, implicit $m0, implicit $exec :: (load 4 from %ir.ptr.0)
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DS_WRITE_B32 %1, killed %2, 64, 0, implicit $m0, implicit $exec :: (store 4 into %ir.ptr.64)
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; Make this load unmergeable, to tempt SILoadStoreOptimizer into merging the
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; other two loads.
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%6:vreg_64 = DS_READ2_B32 %1, 16, 17, 0, implicit $m0, implicit $exec :: (load 8 from %ir.ptr.64, align 4)
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%3:vgpr_32 = COPY %6.sub0
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%4:vgpr_32 = DS_READ_B32 %1, 4, 0, implicit $m0, implicit $exec :: (load 4 from %ir.ptr.4)
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%5:vgpr_32 = V_ADD_CO_U32_e32 killed %3, killed %4, implicit-def $vcc, implicit $exec
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DS_WRITE_B32 killed %1, %5, 0, 0, implicit killed $m0, implicit $exec :: (store 4 into %ir.ptr.0)
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S_ENDPGM 0
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...
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---
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# Make sure the asm def isn't moved after the point where it's used for
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# the address.
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# CHECK-LABEL: name: asm_defines_address
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# CHECK: DS_READ2ST64_B32
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# CHECK: DS_READ2ST64_B32
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# CHECK: INLINEASM
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# CHECK: DS_READ_B32
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# CHECK: DS_READ_B32
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name: asm_defines_address
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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body: |
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bb.0:
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%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%2:vgpr_32 = DS_READ_B32 %1, 3072, 0, implicit $m0, implicit $exec :: (dereferenceable load 4 from `i32 addrspace(3)* getelementptr inbounds ([256 x i32], [256 x i32] addrspace(3)* @lds0, i32 0, i32 0)`, addrspace 3)
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%3:vgpr_32 = DS_READ_B32 %1, 2048, 0, implicit $m0, implicit $exec :: (load 4 from `i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds1, i32 0, i32 undef)`, addrspace 3)
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%4:vgpr_32 = DS_READ_B32 %1, 1024, 0, implicit $m0, implicit $exec :: (load 4 from `i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds3, i32 0, i32 undef)`, addrspace 3)
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INLINEASM &"v_or_b32 $0, 0, $1", 32, 327690, def %0, 327689, %4
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%5:vgpr_32 = DS_READ_B32 %0, 2048, 0, implicit $m0, implicit $exec :: (load 4 from %ir.tmp12, addrspace 3)
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%6:vgpr_32 = DS_READ_B32 %5, 2048, 0, implicit $m0, implicit $exec :: (load 4 from %ir.tmp21, addrspace 3)
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%7:vgpr_32 = DS_READ_B32 %1, 0, 0, implicit $m0, implicit $exec :: (load 4 from `i32 addrspace(3)* getelementptr ([256 x i32], [256 x i32] addrspace(3)* @lds2, i32 0, i32 undef)`, addrspace 3)
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S_SETPC_B64_return undef $sgpr30_sgpr31, implicit %6, implicit %7
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...
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---
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# Make sure Write-after-Write hazards are correctly detected and the
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# instructions moved accordingly.
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# operations.
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# CHECK-LABEL: name: move_waw_hazards
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# CHECK: S_AND_B64
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# CHECK: S_CMP_EQ_U32
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name: move_waw_hazards
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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%3:sgpr_64 = COPY $sgpr0_sgpr1
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%6:sreg_32_xm0_xexec = S_MOV_B32 0
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%7:sreg_32_xm0 = S_MOV_B32 0
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%8:sreg_64_xexec = REG_SEQUENCE killed %6, %subreg.sub0, %7, %subreg.sub1
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%9:sgpr_128 = S_LOAD_DWORDX4_IMM killed %8, 0, 0, 0 :: (invariant load 16, addrspace 6)
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%31:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_IMM %9, 0, 0, 0 :: (dereferenceable invariant load 4)
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%10:sreg_32_xm0_xexec = COPY %31.sub0
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%11:sreg_32_xm0_xexec = COPY killed %31.sub1
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%12:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM %9, 2, 0, 0 :: (dereferenceable invariant load 4)
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%13:sreg_64 = V_CMP_NE_U32_e64 killed %11, 0, implicit $exec
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%15:sreg_64 = V_CMP_NE_U32_e64 killed %12, 0, implicit $exec
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%17:sreg_64_xexec = S_AND_B64 killed %13, killed %15, implicit-def dead $scc
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S_CMP_EQ_U32 killed %10, 0, implicit-def $scc
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%18:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM %9, 3, 0, 0 :: (dereferenceable invariant load 4)
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S_ENDPGM 0
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...
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---
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# CHECK-LABEL: merge_mmos
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# CHECK: S_BUFFER_LOAD_DWORDX2_IMM %0, 0, 0, 0 :: (dereferenceable invariant load 8, align 4)
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# CHECK: BUFFER_LOAD_DWORDX2_OFFSET %0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8, align 4)
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# CHECK: BUFFER_STORE_DWORDX2_OFFSET_exact killed %{{[0-9]+}}, %0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8, align 4)
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# CHECK: BUFFER_LOAD_DWORDX2_OFFSET %0, 0, 64, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 8 from %ir.ptr_addr1 + 64, align 4
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# CHECK: BUFFER_STORE_DWORDX2_OFFSET_exact killed %{{[0-9]+}}, %0, 0, 64, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into %ir.ptr_addr1 + 64, align 4
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name: merge_mmos
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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%0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM %0, 0, 0, 0 :: (dereferenceable invariant load 4)
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%2:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM %0, 1, 0, 0 :: (dereferenceable invariant load 4)
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%3:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET %0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4)
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%4:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET %0, 0, 4, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4)
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BUFFER_STORE_DWORD_OFFSET_exact %3, %0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4)
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BUFFER_STORE_DWORD_OFFSET_exact %4, %0, 0, 4, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4)
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%5:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET %0, 0, 64, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from %ir.ptr_addr1 + 64)
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%6:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET %0, 0, 68, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from %ir.ptr_addr1 + 68)
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BUFFER_STORE_DWORD_OFFSET_exact %5, %0, 0, 64, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into %ir.ptr_addr1 + 64)
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BUFFER_STORE_DWORD_OFFSET_exact %6, %0, 0, 68, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into %ir.ptr_addr1 + 68)
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S_ENDPGM 0
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...
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---
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# CHECK-LABEL: reorder_offsets
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# CHECK-DAG: BUFFER_STORE_DWORDX2_OFFSET_exact killed %{{[0-9]+}}, %0, 0, 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into %ir.reorder_addr1 + 16, align 4, addrspace 1)
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# CHECK-DAG: BUFFER_STORE_DWORDX4_OFFSET_exact killed %{{[0-9]+}}, %0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into %ir.reorder_addr1, align 4, addrspace 1)
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name: reorder_offsets
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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%0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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BUFFER_STORE_DWORD_OFFSET_exact %1, %0, 0, 4, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into %ir.reorder_addr1 + 4)
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BUFFER_STORE_DWORD_OFFSET_exact %1, %0, 0, 8, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into %ir.reorder_addr1 + 8)
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BUFFER_STORE_DWORD_OFFSET_exact %1, %0, 0, 12, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into %ir.reorder_addr1 + 12)
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BUFFER_STORE_DWORD_OFFSET_exact %1, %0, 0, 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into %ir.reorder_addr1 + 16)
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BUFFER_STORE_DWORD_OFFSET_exact %1, %0, 0, 20, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into %ir.reorder_addr1 + 20)
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BUFFER_STORE_DWORD_OFFSET_exact %1, %0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into %ir.reorder_addr1)
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S_ENDPGM 0
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...
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