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92 lines
3.3 KiB
92 lines
3.3 KiB
; RUN: opt -march=hexagon -loop-vectorize -hexagon-autohvx -debug-only=loop-vectorize -S < %s 2>&1 | FileCheck %s
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; REQUIRES: asserts
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; Check that the cost model makes vectorization non-profitable.
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; CHECK: LV: Vectorization is possible but not beneficial
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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define void @f0(i8* nocapture readonly %a0, i8* nocapture %a1, i32 %a2, i32 %a3, i32 %a4, float %a5, float %a6) #0 {
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b0:
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%v0 = icmp sgt i32 %a2, 0
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br i1 %v0, label %b1, label %b2
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b1: ; preds = %b0
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%v1 = add nsw i32 %a3, -1
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%v2 = sitofp i32 %v1 to float
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%v3 = fcmp olt float %v2, %a6
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%v4 = select i1 %v3, float %v2, float %a6
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%v5 = sitofp i32 %a4 to float
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%v6 = fmul float %v4, %v5
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%v7 = sitofp i32 %a2 to float
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%v8 = fmul float %v6, %v7
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%v9 = add nsw i32 %a4, -1
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%v10 = sitofp i32 %v9 to float
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%v11 = fcmp olt float %v10, %a5
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%v12 = select i1 %v11, float %v10, float %a5
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%v13 = fmul float %v12, %v7
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%v14 = fadd float %v13, %v8
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%v15 = fptosi float %v14 to i32
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%v16 = fadd float %a5, 1.000000e+00
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%v17 = fcmp ogt float %v16, %v10
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%v18 = select i1 %v17, float %v10, float %v16
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%v19 = fmul float %v18, %v7
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%v20 = fadd float %v19, %v8
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%v21 = fptosi float %v20 to i32
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%v22 = fadd float %a6, 1.000000e+00
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%v23 = fcmp ogt float %v22, %v2
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%v24 = select i1 %v23, float %v2, float %v22
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%v25 = fmul float %v24, %v5
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%v26 = fmul float %v25, %v7
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%v27 = fadd float %v13, %v26
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%v28 = fptosi float %v27 to i32
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%v29 = fadd float %v19, %v26
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%v30 = fptosi float %v29 to i32
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br label %b3
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b2: ; preds = %b3, %b0
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ret void
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b3: ; preds = %b3, %b1
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%v31 = phi i32 [ 0, %b1 ], [ %v60, %b3 ]
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%v32 = add nsw i32 %v31, %v15
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%v33 = getelementptr inbounds i8, i8* %a0, i32 %v32
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%v34 = load i8, i8* %v33, align 1, !tbaa !0
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%v35 = add nsw i32 %v31, %v21
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%v36 = getelementptr inbounds i8, i8* %a0, i32 %v35
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%v37 = load i8, i8* %v36, align 1, !tbaa !0
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%v38 = add nsw i32 %v31, %v28
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%v39 = getelementptr inbounds i8, i8* %a0, i32 %v38
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%v40 = load i8, i8* %v39, align 1, !tbaa !0
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%v41 = add nsw i32 %v31, %v30
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%v42 = getelementptr inbounds i8, i8* %a0, i32 %v41
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%v43 = load i8, i8* %v42, align 1, !tbaa !0
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%v44 = uitofp i8 %v34 to float
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%v45 = uitofp i8 %v37 to float
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%v46 = uitofp i8 %v40 to float
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%v47 = uitofp i8 %v43 to float
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%v48 = fsub float %v45, %v44
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%v49 = fmul float %v48, 0x3FD99999A0000000
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%v50 = fadd float %v49, %v44
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%v51 = fsub float %v47, %v46
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%v52 = fmul float %v51, 0x3FD99999A0000000
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%v53 = fadd float %v52, %v46
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%v54 = fsub float %v53, %v50
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%v55 = fmul float %v54, 0x3FD99999A0000000
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%v56 = fadd float %v50, %v55
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%v57 = fadd float %v56, 5.000000e-01
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%v58 = fptoui float %v57 to i8
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%v59 = getelementptr inbounds i8, i8* %a1, i32 %v31
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store i8 %v58, i8* %v59, align 1, !tbaa !0
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%v60 = add nuw nsw i32 %v31, 1
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%v61 = icmp eq i32 %v60, %a2
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br i1 %v61, label %b2, label %b3
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}
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attributes #0 = { norecurse nounwind "target-cpu"="hexagonv65" "target-features"="+hvx-length128b,+hvxv65" }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"omnipotent char", !2, i64 0}
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!2 = !{!"Simple C/C++ TBAA"}
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