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117 lines
4.0 KiB
117 lines
4.0 KiB
; RUN: llc -march=hexagon -O3 < %s | FileCheck %s
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; Check if all or's in the loop were predicated.
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; CHECK: if{{.*}} = or
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; CHECK: if{{.*}} = or
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; CHECK: if{{.*}} = or
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; CHECK: if{{.*}} = or
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; CHECK: endloop
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @f0(i32 %a0, i32* nocapture %a1, i32* nocapture %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6) #0 {
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b0:
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%v0 = icmp ugt i32 %a0, 32
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%v1 = lshr i32 %a0, 6
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%v2 = select i1 %v0, i32 %v1, i32 1
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%v3 = icmp eq i32 %v2, 0
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br i1 %v3, label %b9, label %b1
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b1: ; preds = %b0
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%v4 = lshr i32 %a0, 2
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%v5 = getelementptr inbounds i32, i32* %a1, i32 %v4
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br label %b2
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b2: ; preds = %b7, %b1
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%v6 = phi i32* [ %v5, %b1 ], [ %v9, %b7 ]
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%v7 = phi i32* [ %a1, %b1 ], [ %v49, %b7 ]
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%v8 = phi i32 [ 0, %b1 ], [ %v55, %b7 ]
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%v9 = getelementptr i32, i32* %v6, i32 64
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br label %b3
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b3: ; preds = %b3, %b2
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%v10 = phi i32 [ 2, %b2 ], [ %v46, %b3 ]
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%v11 = phi i32 [ 1, %b2 ], [ %v45, %b3 ]
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%v12 = phi i32* [ %v6, %b2 ], [ %v23, %b3 ]
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%v13 = phi i32* [ %v7, %b2 ], [ %v19, %b3 ]
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%v14 = phi i32 [ 0, %b2 ], [ %v47, %b3 ]
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%v15 = phi i32 [ 0, %b2 ], [ %v41, %b3 ]
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%v16 = phi i32 [ 0, %b2 ], [ %v44, %b3 ]
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%v17 = getelementptr inbounds i32, i32* %v13, i32 1
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%v18 = load i32, i32* %v13, align 4, !tbaa !0
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%v19 = getelementptr inbounds i32, i32* %v13, i32 2
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%v20 = load i32, i32* %v17, align 4, !tbaa !0
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%v21 = getelementptr inbounds i32, i32* %v12, i32 1
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%v22 = load i32, i32* %v12, align 4, !tbaa !0
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%v23 = getelementptr inbounds i32, i32* %v12, i32 2
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%v24 = load i32, i32* %v21, align 4, !tbaa !0
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%v25 = tail call i32 @llvm.hexagon.A2.add(i32 %v22, i32 %a4)
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%v26 = tail call i32 @llvm.hexagon.A2.sub(i32 %v25, i32 %a3)
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%v27 = tail call i32 @llvm.hexagon.A2.add(i32 %v24, i32 %a4)
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%v28 = tail call i32 @llvm.hexagon.A2.sub(i32 %v27, i32 %a3)
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%v29 = tail call i32 @llvm.hexagon.A2.sub(i32 %v18, i32 %a5)
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%v30 = tail call i32 @llvm.hexagon.A2.add(i32 %v29, i32 %a6)
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%v31 = tail call i32 @llvm.hexagon.A2.sub(i32 %v20, i32 %a5)
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%v32 = tail call i32 @llvm.hexagon.A2.add(i32 %v31, i32 %a6)
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%v33 = icmp ugt i32 %v26, %v18
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%v34 = select i1 %v33, i32 0, i32 %v11
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%v35 = or i32 %v34, %v15
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%v36 = icmp ult i32 %v30, %v22
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%v37 = select i1 %v36, i32 %v11, i32 0
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%v38 = or i32 %v37, %v16
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%v39 = icmp ugt i32 %v28, %v20
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%v40 = select i1 %v39, i32 0, i32 %v10
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%v41 = or i32 %v35, %v40
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%v42 = icmp ult i32 %v32, %v24
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%v43 = select i1 %v42, i32 %v10, i32 0
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%v44 = or i32 %v38, %v43
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%v45 = shl i32 %v11, 2
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%v46 = shl i32 %v10, 2
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%v47 = add i32 %v14, 1
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%v48 = icmp eq i32 %v47, 32
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br i1 %v48, label %b4, label %b3
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b4: ; preds = %b3
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%v49 = getelementptr i32, i32* %v7, i32 64
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br i1 %v0, label %b5, label %b6
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b5: ; preds = %b4
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%v50 = getelementptr inbounds i32, i32* %a2, i32 %v8
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store i32 %v41, i32* %v50, align 4, !tbaa !0
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%v51 = add i32 %v8, %v2
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%v52 = getelementptr inbounds i32, i32* %a2, i32 %v51
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store i32 %v44, i32* %v52, align 4, !tbaa !0
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br label %b7
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b6: ; preds = %b4
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%v53 = or i32 %v41, %v44
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%v54 = getelementptr inbounds i32, i32* %a2, i32 %v8
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store i32 %v53, i32* %v54, align 4, !tbaa !0
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br label %b7
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b7: ; preds = %b6, %b5
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%v55 = add i32 %v8, 1
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%v56 = icmp eq i32 %v55, %v2
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br i1 %v56, label %b8, label %b2
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b8: ; preds = %b7
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br label %b9
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b9: ; preds = %b8, %b0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.sub(i32, i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.add(i32, i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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attributes #1 = { nounwind readnone }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"int", !2}
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!2 = !{!"omnipotent char", !3}
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!3 = !{!"Simple C/C++ TBAA"}
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