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68 lines
1.9 KiB
68 lines
1.9 KiB
; RUN: llc -march=hexagon -hexagon-hwloop-preheader < %s
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; REQUIRES: asserts
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; Checks that a subreg in a Phi is propagated correctly when a
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; new preheader is created in the Hardware Loop pass.
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; Function Attrs: nounwind
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define void @f0() #0 {
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b0:
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br label %b2
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b1: ; preds = %b2, %b1
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%v0 = or i64 0, undef
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%v1 = add nsw i64 0, %v0
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%v2 = add nsw i64 %v1, 0
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%v3 = add nsw i64 %v2, 0
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%v4 = add nsw i64 %v3, 0
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%v5 = add nsw i64 %v4, 0
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%v6 = add nsw i64 %v5, 0
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%v7 = load i32, i32* undef, align 4
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%v8 = ashr i32 %v7, 5
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%v9 = sext i32 %v8 to i64
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%v10 = mul nsw i64 %v9, %v9
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%v11 = add nsw i64 %v6, %v10
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%v12 = add nsw i64 %v11, 0
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%v13 = add nsw i64 0, %v12
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%v14 = add nsw i64 %v13, 0
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%v15 = add nsw i64 %v14, 0
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%v16 = add nsw i64 %v15, 0
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%v17 = add nsw i64 %v16, 0
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%v18 = add nsw i64 %v17, 0
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%v19 = add nsw i64 %v18, 0
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%v20 = add nsw i64 %v19, 0
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%v21 = lshr i64 %v20, 32
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%v22 = trunc i64 %v21 to i32
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br i1 undef, label %b1, label %b3
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b2: ; preds = %b5, %b0
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br i1 undef, label %b1, label %b4
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b3: ; preds = %b1
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br i1 false, label %b5, label %b4
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b4: ; preds = %b4, %b3, %b2
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%v23 = phi i32 [ %v37, %b4 ], [ undef, %b2 ], [ %v22, %b3 ]
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%v24 = zext i32 %v23 to i64
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%v25 = shl nuw i64 %v24, 32
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%v26 = or i64 %v25, 0
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%v27 = add nsw i64 0, %v26
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%v28 = add nsw i64 %v27, 0
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%v29 = add nsw i64 %v28, 0
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%v30 = add nsw i64 %v29, 0
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%v31 = add nsw i64 %v30, 0
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%v32 = add nsw i64 %v31, 0
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%v33 = add nsw i64 %v32, 0
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%v34 = add nsw i64 %v33, 0
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%v35 = trunc i64 %v34 to i32
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%v36 = lshr i64 %v34, 32
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%v37 = trunc i64 %v36 to i32
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%v38 = icmp slt i32 undef, undef
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br i1 %v38, label %b4, label %b5
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b5: ; preds = %b4, %b3
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br label %b2
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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