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44 lines
1.6 KiB
44 lines
1.6 KiB
; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=1 < %s -pipeliner-experimental-cg=true | FileCheck %s
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; Test that we update the offset correctly for loads that are
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; moved past stores. In these cases, we change the dependences
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; to make it easier to move the instructions, and we have to update
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; the register/offsets correctly after the schedule is finalized.
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@g0 = common global [400 x i32] zeroinitializer, align 8
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@g1 = common global [400 x i32] zeroinitializer, align 8
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; Function Attrs: nounwind
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define void @f0() #0 {
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b0:
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br label %b2
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b1: ; preds = %b2
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ret void
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; CHECK: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: = memd([[REG1:(r[0-9]+)]]+#8)
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; CHECK: memd([[REG1]]++#8) =
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; CHECK: }{{[ \t]*}}:endloop
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b2: ; preds = %b2, %b0
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%v0 = phi i32* [ getelementptr inbounds ([400 x i32], [400 x i32]* @g0, i32 0, i32 0), %b0 ], [ %v11, %b2 ]
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%v1 = phi i32* [ getelementptr inbounds ([400 x i32], [400 x i32]* @g1, i32 0, i32 0), %b0 ], [ %v12, %b2 ]
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%v2 = phi i32 [ 0, %b0 ], [ %v9, %b2 ]
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%v3 = bitcast i32* %v0 to <2 x i32>*
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%v4 = load <2 x i32>, <2 x i32>* %v3, align 8
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%v5 = mul <2 x i32> %v4, <i32 7, i32 7>
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%v6 = bitcast i32* %v1 to <2 x i32>*
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%v7 = load <2 x i32>, <2 x i32>* %v6, align 8
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%v8 = add <2 x i32> %v7, %v5
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store <2 x i32> %v8, <2 x i32>* %v6, align 8
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%v9 = add nsw i32 %v2, 2
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%v10 = icmp slt i32 %v2, 398
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%v11 = getelementptr i32, i32* %v0, i32 2
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%v12 = getelementptr i32, i32* %v1, i32 2
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br i1 %v10, label %b2, label %b1
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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