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133 lines
6.3 KiB
133 lines
6.3 KiB
; RUN: llc -march=hexagon -enable-pipeliner=false < %s | FileCheck %s
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; Test that the vsplat and vmemu are not all serialized due to chain edges
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; caused by the hasSideEffects flag. The exact code generation may change
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; due to the scheduling changes, but we shouldn't see a series of
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; vsplat and vmemu instructions that each occur in a single packet.
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; CHECK: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: vsplat
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; CHECK-NEXT: vsplat
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; CHECK: vsplat
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; CHECK-NEXT: vsplat
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; CHECK: endloop0
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@g0 = global [256 x i8] c"^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^00226644,,..**8888::66,,,,&&^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^22000022..4444>>::8888**..^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^<<66220000226644<<>>::^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^>><<446622000022>>", align 64
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; Function Attrs: nounwind
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define void @f0(i16** noalias nocapture readonly %a0, i16* noalias nocapture readonly %a1, i32* noalias nocapture %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6) #0 {
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b0:
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%v0 = load <16 x i32>, <16 x i32>* bitcast ([256 x i8]* @g0 to <16 x i32>*), align 64, !tbaa !0
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%v1 = load <16 x i32>, <16 x i32>* bitcast (i8* getelementptr inbounds ([256 x i8], [256 x i8]* @g0, i32 0, i32 64) to <16 x i32>*), align 64, !tbaa !0
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%v2 = load <16 x i32>, <16 x i32>* bitcast (i8* getelementptr inbounds ([256 x i8], [256 x i8]* @g0, i32 0, i32 128) to <16 x i32>*), align 64, !tbaa !0
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%v3 = load <16 x i32>, <16 x i32>* bitcast (i8* getelementptr inbounds ([256 x i8], [256 x i8]* @g0, i32 0, i32 192) to <16 x i32>*), align 64, !tbaa !0
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%v4 = icmp sgt i32 %a5, 0
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br i1 %v4, label %b1, label %b5
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b1: ; preds = %b0
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%v5 = bitcast i32* %a2 to <16 x i32>*
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%v6 = tail call <16 x i32> @llvm.hexagon.V6.vd0()
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%v7 = bitcast i16* %a1 to i64*
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%v8 = mul nsw i32 %a3, 4
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%v9 = add i32 %v8, %a6
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%v10 = add i32 %v9, 32
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%v11 = add i32 %a5, -1
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br label %b2
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b2: ; preds = %b4, %b1
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%v12 = phi i32 [ 0, %b1 ], [ %v59, %b4 ]
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%v13 = phi <16 x i32>* [ %v5, %b1 ], [ %v58, %b4 ]
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%v14 = getelementptr i16*, i16** %a0, i32 %v12
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br label %b3
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b3: ; preds = %b3, %b2
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%v15 = phi i16** [ %v14, %b2 ], [ %v57, %b3 ]
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%v16 = phi i32 [ 0, %b2 ], [ %v55, %b3 ]
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%v17 = phi i64* [ %v7, %b2 ], [ %v23, %b3 ]
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%v18 = phi <16 x i32> [ %v6, %b2 ], [ %v54, %b3 ]
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%v19 = load i16*, i16** %v15, align 4, !tbaa !3
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%v20 = getelementptr inbounds i16, i16* %v19, i32 %v9
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%v21 = getelementptr inbounds i64, i64* %v17, i32 1
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%v22 = load i64, i64* %v17, align 8, !tbaa !0
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%v23 = getelementptr inbounds i64, i64* %v17, i32 2
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%v24 = load i64, i64* %v21, align 8, !tbaa !0
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%v25 = trunc i64 %v22 to i32
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%v26 = lshr i64 %v22, 32
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%v27 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v25)
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%v28 = trunc i64 %v26 to i32
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%v29 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v28)
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%v30 = trunc i64 %v24 to i32
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%v31 = lshr i64 %v24, 32
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%v32 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v30)
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%v33 = trunc i64 %v31 to i32
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%v34 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v33)
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%v35 = bitcast i16* %v20 to <16 x i32>*
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%v36 = load <16 x i32>, <16 x i32>* %v35, align 4, !tbaa !0
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%v37 = getelementptr inbounds i16, i16* %v19, i32 %v10
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%v38 = bitcast i16* %v37 to <16 x i32>*
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%v39 = load <16 x i32>, <16 x i32>* %v38, align 4, !tbaa !0
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%v40 = tail call <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32> %v39, <16 x i32> %v36)
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%v41 = tail call <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32> %v40, <16 x i32> %v40)
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%v42 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v0)
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%v43 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v1)
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%v44 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v2)
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%v45 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v3)
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%v46 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v27, <16 x i32> %v42)
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%v47 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v29, <16 x i32> %v43)
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%v48 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v32, <16 x i32> %v44)
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%v49 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v34, <16 x i32> %v45)
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%v50 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32> %v46, <16 x i32> %v46)
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%v51 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32> %v50, <16 x i32> %v47, <16 x i32> %v47)
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%v52 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32> %v51, <16 x i32> %v48, <16 x i32> %v48)
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%v53 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32> %v52, <16 x i32> %v49, <16 x i32> %v49)
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%v54 = tail call <16 x i32> @llvm.hexagon.V6.vasrw.acc(<16 x i32> %v18, <16 x i32> %v53, i32 6)
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%v55 = add nsw i32 %v16, 1
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%v56 = icmp eq i32 %v16, 7
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%v57 = getelementptr i16*, i16** %v15, i32 1
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br i1 %v56, label %b4, label %b3
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b4: ; preds = %b3
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%v58 = getelementptr inbounds <16 x i32>, <16 x i32>* %v13, i32 1
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store <16 x i32> %v54, <16 x i32>* %v13, align 64, !tbaa !0
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%v59 = add nsw i32 %v12, 1
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%v60 = icmp eq i32 %v12, %v11
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br i1 %v60, label %b5, label %b2
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b5: ; preds = %b4, %b0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vd0() #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vasrw.acc(<16 x i32>, <16 x i32>, i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"omnipotent char", !2, i64 0}
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!2 = !{!"Simple C/C++ TBAA"}
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!3 = !{!4, !4, i64 0}
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!4 = !{!"any pointer", !1, i64 0}
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