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422 lines
12 KiB
422 lines
12 KiB
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
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define half @select_fcmp_false(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: select_fcmp_false:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmv.h fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: select_fcmp_false:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = fcmp false half %a, %b
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%2 = select i1 %1, half %a, half %b
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ret half %2
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}
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define half @select_fcmp_oeq(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: select_fcmp_oeq:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: feq.h a0, fa0, fa1
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; RV32IZFH-NEXT: bnez a0, .LBB1_2
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; RV32IZFH-NEXT: # %bb.1:
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; RV32IZFH-NEXT: fmv.h fa0, fa1
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; RV32IZFH-NEXT: .LBB1_2:
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: select_fcmp_oeq:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: feq.h a0, fa0, fa1
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; RV64IZFH-NEXT: bnez a0, .LBB1_2
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; RV64IZFH-NEXT: # %bb.1:
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; RV64IZFH-NEXT: fmv.h fa0, fa1
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; RV64IZFH-NEXT: .LBB1_2:
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; RV64IZFH-NEXT: ret
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%1 = fcmp oeq half %a, %b
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%2 = select i1 %1, half %a, half %b
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ret half %2
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}
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define half @select_fcmp_ogt(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: select_fcmp_ogt:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: flt.h a0, fa1, fa0
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; RV32IZFH-NEXT: bnez a0, .LBB2_2
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; RV32IZFH-NEXT: # %bb.1:
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; RV32IZFH-NEXT: fmv.h fa0, fa1
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; RV32IZFH-NEXT: .LBB2_2:
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: select_fcmp_ogt:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: flt.h a0, fa1, fa0
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; RV64IZFH-NEXT: bnez a0, .LBB2_2
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; RV64IZFH-NEXT: # %bb.1:
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; RV64IZFH-NEXT: fmv.h fa0, fa1
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; RV64IZFH-NEXT: .LBB2_2:
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; RV64IZFH-NEXT: ret
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%1 = fcmp ogt half %a, %b
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%2 = select i1 %1, half %a, half %b
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ret half %2
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}
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define half @select_fcmp_oge(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: select_fcmp_oge:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fle.h a0, fa1, fa0
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; RV32IZFH-NEXT: bnez a0, .LBB3_2
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; RV32IZFH-NEXT: # %bb.1:
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; RV32IZFH-NEXT: fmv.h fa0, fa1
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; RV32IZFH-NEXT: .LBB3_2:
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: select_fcmp_oge:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fle.h a0, fa1, fa0
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; RV64IZFH-NEXT: bnez a0, .LBB3_2
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; RV64IZFH-NEXT: # %bb.1:
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; RV64IZFH-NEXT: fmv.h fa0, fa1
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; RV64IZFH-NEXT: .LBB3_2:
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; RV64IZFH-NEXT: ret
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%1 = fcmp oge half %a, %b
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%2 = select i1 %1, half %a, half %b
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ret half %2
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}
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define half @select_fcmp_olt(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: select_fcmp_olt:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: flt.h a0, fa0, fa1
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; RV32IZFH-NEXT: bnez a0, .LBB4_2
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; RV32IZFH-NEXT: # %bb.1:
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; RV32IZFH-NEXT: fmv.h fa0, fa1
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; RV32IZFH-NEXT: .LBB4_2:
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: select_fcmp_olt:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: flt.h a0, fa0, fa1
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; RV64IZFH-NEXT: bnez a0, .LBB4_2
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; RV64IZFH-NEXT: # %bb.1:
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; RV64IZFH-NEXT: fmv.h fa0, fa1
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; RV64IZFH-NEXT: .LBB4_2:
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; RV64IZFH-NEXT: ret
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%1 = fcmp olt half %a, %b
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%2 = select i1 %1, half %a, half %b
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ret half %2
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}
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define half @select_fcmp_ole(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: select_fcmp_ole:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fle.h a0, fa0, fa1
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; RV32IZFH-NEXT: bnez a0, .LBB5_2
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; RV32IZFH-NEXT: # %bb.1:
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; RV32IZFH-NEXT: fmv.h fa0, fa1
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; RV32IZFH-NEXT: .LBB5_2:
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: select_fcmp_ole:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fle.h a0, fa0, fa1
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; RV64IZFH-NEXT: bnez a0, .LBB5_2
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; RV64IZFH-NEXT: # %bb.1:
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; RV64IZFH-NEXT: fmv.h fa0, fa1
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; RV64IZFH-NEXT: .LBB5_2:
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; RV64IZFH-NEXT: ret
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%1 = fcmp ole half %a, %b
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%2 = select i1 %1, half %a, half %b
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ret half %2
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}
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define half @select_fcmp_one(half %a, half %b) nounwind {
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; TODO: feq.h+sltiu+bne sequence could be optimised
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; RV32IZFH-LABEL: select_fcmp_one:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: feq.h a0, fa1, fa1
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; RV32IZFH-NEXT: feq.h a1, fa0, fa0
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; RV32IZFH-NEXT: and a0, a1, a0
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; RV32IZFH-NEXT: feq.h a1, fa0, fa1
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; RV32IZFH-NEXT: not a1, a1
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; RV32IZFH-NEXT: and a0, a1, a0
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; RV32IZFH-NEXT: bnez a0, .LBB6_2
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; RV32IZFH-NEXT: # %bb.1:
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; RV32IZFH-NEXT: fmv.h fa0, fa1
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; RV32IZFH-NEXT: .LBB6_2:
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: select_fcmp_one:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: feq.h a0, fa1, fa1
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; RV64IZFH-NEXT: feq.h a1, fa0, fa0
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; RV64IZFH-NEXT: and a0, a1, a0
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; RV64IZFH-NEXT: feq.h a1, fa0, fa1
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; RV64IZFH-NEXT: not a1, a1
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; RV64IZFH-NEXT: and a0, a1, a0
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; RV64IZFH-NEXT: bnez a0, .LBB6_2
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; RV64IZFH-NEXT: # %bb.1:
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; RV64IZFH-NEXT: fmv.h fa0, fa1
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; RV64IZFH-NEXT: .LBB6_2:
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; RV64IZFH-NEXT: ret
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%1 = fcmp one half %a, %b
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%2 = select i1 %1, half %a, half %b
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ret half %2
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}
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define half @select_fcmp_ord(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: select_fcmp_ord:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: feq.h a0, fa1, fa1
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; RV32IZFH-NEXT: feq.h a1, fa0, fa0
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; RV32IZFH-NEXT: and a0, a1, a0
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; RV32IZFH-NEXT: bnez a0, .LBB7_2
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; RV32IZFH-NEXT: # %bb.1:
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; RV32IZFH-NEXT: fmv.h fa0, fa1
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; RV32IZFH-NEXT: .LBB7_2:
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: select_fcmp_ord:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: feq.h a0, fa1, fa1
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; RV64IZFH-NEXT: feq.h a1, fa0, fa0
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; RV64IZFH-NEXT: and a0, a1, a0
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; RV64IZFH-NEXT: bnez a0, .LBB7_2
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; RV64IZFH-NEXT: # %bb.1:
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; RV64IZFH-NEXT: fmv.h fa0, fa1
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; RV64IZFH-NEXT: .LBB7_2:
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; RV64IZFH-NEXT: ret
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%1 = fcmp ord half %a, %b
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%2 = select i1 %1, half %a, half %b
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ret half %2
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}
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define half @select_fcmp_ueq(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: select_fcmp_ueq:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: feq.h a0, fa0, fa1
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; RV32IZFH-NEXT: feq.h a1, fa1, fa1
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; RV32IZFH-NEXT: feq.h a2, fa0, fa0
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; RV32IZFH-NEXT: and a1, a2, a1
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; RV32IZFH-NEXT: seqz a1, a1
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; RV32IZFH-NEXT: or a0, a0, a1
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; RV32IZFH-NEXT: bnez a0, .LBB8_2
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; RV32IZFH-NEXT: # %bb.1:
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; RV32IZFH-NEXT: fmv.h fa0, fa1
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; RV32IZFH-NEXT: .LBB8_2:
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: select_fcmp_ueq:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: feq.h a0, fa0, fa1
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; RV64IZFH-NEXT: feq.h a1, fa1, fa1
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; RV64IZFH-NEXT: feq.h a2, fa0, fa0
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; RV64IZFH-NEXT: and a1, a2, a1
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; RV64IZFH-NEXT: seqz a1, a1
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; RV64IZFH-NEXT: or a0, a0, a1
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; RV64IZFH-NEXT: bnez a0, .LBB8_2
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; RV64IZFH-NEXT: # %bb.1:
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; RV64IZFH-NEXT: fmv.h fa0, fa1
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; RV64IZFH-NEXT: .LBB8_2:
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; RV64IZFH-NEXT: ret
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%1 = fcmp ueq half %a, %b
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%2 = select i1 %1, half %a, half %b
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ret half %2
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}
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define half @select_fcmp_ugt(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: select_fcmp_ugt:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fle.h a0, fa0, fa1
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; RV32IZFH-NEXT: xori a0, a0, 1
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; RV32IZFH-NEXT: bnez a0, .LBB9_2
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; RV32IZFH-NEXT: # %bb.1:
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; RV32IZFH-NEXT: fmv.h fa0, fa1
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; RV32IZFH-NEXT: .LBB9_2:
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: select_fcmp_ugt:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fle.h a0, fa0, fa1
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; RV64IZFH-NEXT: xori a0, a0, 1
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; RV64IZFH-NEXT: bnez a0, .LBB9_2
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; RV64IZFH-NEXT: # %bb.1:
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; RV64IZFH-NEXT: fmv.h fa0, fa1
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; RV64IZFH-NEXT: .LBB9_2:
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; RV64IZFH-NEXT: ret
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%1 = fcmp ugt half %a, %b
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%2 = select i1 %1, half %a, half %b
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ret half %2
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}
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define half @select_fcmp_uge(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: select_fcmp_uge:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: flt.h a0, fa0, fa1
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; RV32IZFH-NEXT: xori a0, a0, 1
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; RV32IZFH-NEXT: bnez a0, .LBB10_2
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; RV32IZFH-NEXT: # %bb.1:
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; RV32IZFH-NEXT: fmv.h fa0, fa1
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; RV32IZFH-NEXT: .LBB10_2:
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: select_fcmp_uge:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: flt.h a0, fa0, fa1
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; RV64IZFH-NEXT: xori a0, a0, 1
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; RV64IZFH-NEXT: bnez a0, .LBB10_2
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; RV64IZFH-NEXT: # %bb.1:
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; RV64IZFH-NEXT: fmv.h fa0, fa1
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; RV64IZFH-NEXT: .LBB10_2:
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; RV64IZFH-NEXT: ret
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%1 = fcmp uge half %a, %b
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%2 = select i1 %1, half %a, half %b
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ret half %2
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}
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define half @select_fcmp_ult(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: select_fcmp_ult:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fle.h a0, fa1, fa0
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; RV32IZFH-NEXT: xori a0, a0, 1
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; RV32IZFH-NEXT: bnez a0, .LBB11_2
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; RV32IZFH-NEXT: # %bb.1:
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; RV32IZFH-NEXT: fmv.h fa0, fa1
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; RV32IZFH-NEXT: .LBB11_2:
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: select_fcmp_ult:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fle.h a0, fa1, fa0
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; RV64IZFH-NEXT: xori a0, a0, 1
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; RV64IZFH-NEXT: bnez a0, .LBB11_2
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; RV64IZFH-NEXT: # %bb.1:
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; RV64IZFH-NEXT: fmv.h fa0, fa1
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; RV64IZFH-NEXT: .LBB11_2:
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; RV64IZFH-NEXT: ret
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%1 = fcmp ult half %a, %b
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%2 = select i1 %1, half %a, half %b
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ret half %2
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}
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define half @select_fcmp_ule(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: select_fcmp_ule:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: flt.h a0, fa1, fa0
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; RV32IZFH-NEXT: xori a0, a0, 1
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; RV32IZFH-NEXT: bnez a0, .LBB12_2
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; RV32IZFH-NEXT: # %bb.1:
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; RV32IZFH-NEXT: fmv.h fa0, fa1
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; RV32IZFH-NEXT: .LBB12_2:
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: select_fcmp_ule:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: flt.h a0, fa1, fa0
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; RV64IZFH-NEXT: xori a0, a0, 1
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; RV64IZFH-NEXT: bnez a0, .LBB12_2
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; RV64IZFH-NEXT: # %bb.1:
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; RV64IZFH-NEXT: fmv.h fa0, fa1
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; RV64IZFH-NEXT: .LBB12_2:
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; RV64IZFH-NEXT: ret
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%1 = fcmp ule half %a, %b
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%2 = select i1 %1, half %a, half %b
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ret half %2
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}
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define half @select_fcmp_une(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: select_fcmp_une:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: feq.h a0, fa0, fa1
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; RV32IZFH-NEXT: xori a0, a0, 1
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; RV32IZFH-NEXT: bnez a0, .LBB13_2
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; RV32IZFH-NEXT: # %bb.1:
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; RV32IZFH-NEXT: fmv.h fa0, fa1
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; RV32IZFH-NEXT: .LBB13_2:
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: select_fcmp_une:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: feq.h a0, fa0, fa1
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; RV64IZFH-NEXT: xori a0, a0, 1
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; RV64IZFH-NEXT: bnez a0, .LBB13_2
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; RV64IZFH-NEXT: # %bb.1:
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; RV64IZFH-NEXT: fmv.h fa0, fa1
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; RV64IZFH-NEXT: .LBB13_2:
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; RV64IZFH-NEXT: ret
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%1 = fcmp une half %a, %b
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%2 = select i1 %1, half %a, half %b
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ret half %2
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}
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define half @select_fcmp_uno(half %a, half %b) nounwind {
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; TODO: sltiu+bne could be optimized
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; RV32IZFH-LABEL: select_fcmp_uno:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: feq.h a0, fa1, fa1
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; RV32IZFH-NEXT: feq.h a1, fa0, fa0
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; RV32IZFH-NEXT: and a0, a1, a0
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; RV32IZFH-NEXT: seqz a0, a0
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; RV32IZFH-NEXT: bnez a0, .LBB14_2
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; RV32IZFH-NEXT: # %bb.1:
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; RV32IZFH-NEXT: fmv.h fa0, fa1
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; RV32IZFH-NEXT: .LBB14_2:
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: select_fcmp_uno:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: feq.h a0, fa1, fa1
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; RV64IZFH-NEXT: feq.h a1, fa0, fa0
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; RV64IZFH-NEXT: and a0, a1, a0
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; RV64IZFH-NEXT: seqz a0, a0
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; RV64IZFH-NEXT: bnez a0, .LBB14_2
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; RV64IZFH-NEXT: # %bb.1:
|
|
; RV64IZFH-NEXT: fmv.h fa0, fa1
|
|
; RV64IZFH-NEXT: .LBB14_2:
|
|
; RV64IZFH-NEXT: ret
|
|
%1 = fcmp uno half %a, %b
|
|
%2 = select i1 %1, half %a, half %b
|
|
ret half %2
|
|
}
|
|
|
|
define half @select_fcmp_true(half %a, half %b) nounwind {
|
|
; RV32IZFH-LABEL: select_fcmp_true:
|
|
; RV32IZFH: # %bb.0:
|
|
; RV32IZFH-NEXT: ret
|
|
;
|
|
; RV64IZFH-LABEL: select_fcmp_true:
|
|
; RV64IZFH: # %bb.0:
|
|
; RV64IZFH-NEXT: ret
|
|
%1 = fcmp true half %a, %b
|
|
%2 = select i1 %1, half %a, half %b
|
|
ret half %2
|
|
}
|
|
|
|
; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
|
|
define i32 @i32_select_fcmp_oeq(half %a, half %b, i32 %c, i32 %d) nounwind {
|
|
; RV32IZFH-LABEL: i32_select_fcmp_oeq:
|
|
; RV32IZFH: # %bb.0:
|
|
; RV32IZFH-NEXT: feq.h a2, fa0, fa1
|
|
; RV32IZFH-NEXT: bnez a2, .LBB16_2
|
|
; RV32IZFH-NEXT: # %bb.1:
|
|
; RV32IZFH-NEXT: mv a0, a1
|
|
; RV32IZFH-NEXT: .LBB16_2:
|
|
; RV32IZFH-NEXT: ret
|
|
;
|
|
; RV64IZFH-LABEL: i32_select_fcmp_oeq:
|
|
; RV64IZFH: # %bb.0:
|
|
; RV64IZFH-NEXT: feq.h a2, fa0, fa1
|
|
; RV64IZFH-NEXT: bnez a2, .LBB16_2
|
|
; RV64IZFH-NEXT: # %bb.1:
|
|
; RV64IZFH-NEXT: mv a0, a1
|
|
; RV64IZFH-NEXT: .LBB16_2:
|
|
; RV64IZFH-NEXT: ret
|
|
%1 = fcmp oeq half %a, %b
|
|
%2 = select i1 %1, i32 %c, i32 %d
|
|
ret i32 %2
|
|
}
|