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74 lines
2.3 KiB
74 lines
2.3 KiB
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; This file provides a simple sanity check of half operations for
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; RV32I and RV64I. This is primarily intended to ensure that custom
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; legalisation or DAG combines aren't incorrectly triggered when the Zfh
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; extension isn't enabled.
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define half @half_test(half %a, half %b) nounwind {
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; RV32I-LABEL: half_test:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: sw s1, 4(sp)
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; RV32I-NEXT: sw s2, 0(sp)
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; RV32I-NEXT: mv s2, a1
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; RV32I-NEXT: lui a1, 16
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; RV32I-NEXT: addi s0, a1, -1
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; RV32I-NEXT: and a0, a0, s0
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; RV32I-NEXT: call __gnu_h2f_ieee
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; RV32I-NEXT: mv s1, a0
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; RV32I-NEXT: and a0, s2, s0
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; RV32I-NEXT: call __gnu_h2f_ieee
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; RV32I-NEXT: mv s0, a0
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; RV32I-NEXT: mv a0, s1
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; RV32I-NEXT: mv a1, s0
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; RV32I-NEXT: call __addsf3
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; RV32I-NEXT: mv a1, s0
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; RV32I-NEXT: call __divsf3
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; RV32I-NEXT: call __gnu_f2h_ieee
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; RV32I-NEXT: lw s2, 0(sp)
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; RV32I-NEXT: lw s1, 4(sp)
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: half_test:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -32
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; RV64I-NEXT: sd ra, 24(sp)
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; RV64I-NEXT: sd s0, 16(sp)
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; RV64I-NEXT: sd s1, 8(sp)
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; RV64I-NEXT: sd s2, 0(sp)
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; RV64I-NEXT: mv s2, a1
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; RV64I-NEXT: lui a1, 16
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; RV64I-NEXT: addiw s0, a1, -1
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; RV64I-NEXT: and a0, a0, s0
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; RV64I-NEXT: call __gnu_h2f_ieee
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; RV64I-NEXT: mv s1, a0
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; RV64I-NEXT: and a0, s2, s0
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; RV64I-NEXT: call __gnu_h2f_ieee
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; RV64I-NEXT: mv s0, a0
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; RV64I-NEXT: mv a0, s1
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; RV64I-NEXT: mv a1, s0
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; RV64I-NEXT: call __addsf3
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; RV64I-NEXT: mv a1, s0
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; RV64I-NEXT: call __divsf3
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; RV64I-NEXT: call __gnu_f2h_ieee
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; RV64I-NEXT: ld s2, 0(sp)
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; RV64I-NEXT: ld s1, 8(sp)
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; RV64I-NEXT: ld s0, 16(sp)
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; RV64I-NEXT: ld ra, 24(sp)
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; RV64I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: ret
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%1 = fadd half %a, %b
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%2 = fdiv half %1, %b
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ret half %2
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}
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