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300 lines
9.2 KiB
300 lines
9.2 KiB
; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
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; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
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; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
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; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
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; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
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; Check that the correct save/restore libcalls are generated.
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@var0 = global [18 x i32] zeroinitializer
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@var1 = global [24 x i32] zeroinitializer
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@var2 = global [30 x i32] zeroinitializer
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define void @callee_saved0() nounwind {
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; RV32I-LABEL: callee_saved0:
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; RV32I-NOT: call t0, __riscv_save
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; RV32I-NOT: tail __riscv_restore
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;
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; RV64I-LABEL: callee_saved0:
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; RV64I-NOT: call t0, __riscv_save
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; RV64I-NOT: tail __riscv_restore
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;
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; RV32I-SR-LABEL: callee_saved0:
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; RV32I-SR: call t0, __riscv_save_5
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; RV32I-SR: tail __riscv_restore_5
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;
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; RV64I-SR-LABEL: callee_saved0:
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; RV64I-SR: call t0, __riscv_save_5
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; RV64I-SR: tail __riscv_restore_5
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;
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; RV32I-FP-SR-LABEL: callee_saved0:
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; RV32I-FP-SR: call t0, __riscv_save_5
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; RV32I-FP-SR: tail __riscv_restore_5
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;
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; RV64I-FP-SR-LABEL: callee_saved0:
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; RV64I-FP-SR: call t0, __riscv_save_5
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; RV64I-FP-SR: tail __riscv_restore_5
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%val = load [18 x i32], [18 x i32]* @var0
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store volatile [18 x i32] %val, [18 x i32]* @var0
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ret void
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}
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define void @callee_saved1() nounwind {
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; RV32I-LABEL: callee_saved1:
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; RV32I-NOT: call t0, __riscv_save
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; RV32I-NOT: tail __riscv_restore
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;
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; RV64I-LABEL: callee_saved1:
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; RV64I-NOT: call t0, __riscv_save
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; RV64I-NOT: tail __riscv_restore
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;
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; RV32I-SR-LABEL: callee_saved1:
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; RV32I-SR: call t0, __riscv_save_11
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; RV32I-SR: tail __riscv_restore_11
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;
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; RV64I-SR-LABEL: callee_saved1:
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; RV64I-SR: call t0, __riscv_save_11
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; RV64I-SR: tail __riscv_restore_11
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;
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; RV32I-FP-SR-LABEL: callee_saved1:
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; RV32I-FP-SR: call t0, __riscv_save_11
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; RV32I-FP-SR: tail __riscv_restore_11
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;
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; RV64I-FP-SR-LABEL: callee_saved1:
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; RV64I-FP-SR: call t0, __riscv_save_11
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; RV64I-FP-SR: tail __riscv_restore_11
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%val = load [24 x i32], [24 x i32]* @var1
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store volatile [24 x i32] %val, [24 x i32]* @var1
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ret void
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}
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define void @callee_saved2() nounwind {
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; RV32I-LABEL: callee_saved2:
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; RV32I-NOT: call t0, __riscv_save
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; RV32I-NOT: tail __riscv_restore
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;
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; RV64I-LABEL: callee_saved2:
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; RV64I-NOT: call t0, __riscv_save
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; RV64I-NOT: tail __riscv_restore
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;
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; RV32I-SR-LABEL: callee_saved2:
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; RV32I-SR: call t0, __riscv_save_12
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; RV32I-SR: tail __riscv_restore_12
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;
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; RV64I-SR-LABEL: callee_saved2:
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; RV64I-SR: call t0, __riscv_save_12
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; RV64I-SR: tail __riscv_restore_12
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;
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; RV32I-FP-SR-LABEL: callee_saved2:
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; RV32I-FP-SR: call t0, __riscv_save_12
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; RV32I-FP-SR: tail __riscv_restore_12
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;
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; RV64I-FP-SR-LABEL: callee_saved2:
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; RV64I-FP-SR: call t0, __riscv_save_12
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; RV64I-FP-SR: tail __riscv_restore_12
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%val = load [30 x i32], [30 x i32]* @var2
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store volatile [30 x i32] %val, [30 x i32]* @var2
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ret void
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}
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; Check that floating point callee saved registers are still manually saved and
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; restored.
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define void @callee_saved_fp() nounwind {
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; RV32I-LABEL: callee_saved_fp:
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; RV32I-NOT: call t0, __riscv_save
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; RV32I-NOT: tail __riscv_restore
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;
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; RV64I-LABEL: callee_saved_fp:
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; RV64I-NOT: call t0, __riscv_save
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; RV64I-NOT: tail __riscv_restore
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;
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; RV32I-SR-LABEL: callee_saved_fp:
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; RV32I-SR: call t0, __riscv_save_7
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; RV32I-SR: tail __riscv_restore_7
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;
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; RV64I-SR-LABEL: callee_saved_fp:
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; RV64I-SR: call t0, __riscv_save_7
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; RV64I-SR: tail __riscv_restore_7
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;
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; RV32I-FP-SR-LABEL: callee_saved_fp:
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; RV32I-FP-SR: call t0, __riscv_save_7
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; RV32I-FP-SR-NEXT: addi sp, sp, -16
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; RV32I-FP-SR-NEXT: fsw fs0, 12(sp)
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; RV32I-FP-SR: flw fs0, 12(sp)
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; RV32I-FP-SR-NEXT: addi sp, sp, 16
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; RV32I-FP-SR-NEXT: tail __riscv_restore_7
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;
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; RV64I-FP-SR-LABEL: callee_saved_fp:
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; RV64I-FP-SR: call t0, __riscv_save_7
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; RV64I-FP-SR-NEXT: addi sp, sp, -16
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; RV64I-FP-SR-NEXT: fsd fs0, 8(sp)
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; RV64I-FP-SR: fld fs0, 8(sp)
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; RV64I-FP-SR-NEXT: addi sp, sp, 16
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; RV64I-FP-SR-NEXT: tail __riscv_restore_7
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call void asm sideeffect "", "~{f8},~{x9},~{x18},~{x19},~{x20},~{x21},~{x22}"()
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ret void
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}
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; Check that preserving tail calls is preferred over save/restore
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declare i32 @tail_callee(i32 %i)
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define i32 @tail_call(i32 %i) nounwind {
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; RV32I-LABEL: tail_call:
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; RV32I-NOT: call t0, __riscv_save
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; RV32I: tail tail_callee
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; RV32I-NOT: tail __riscv_restore
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;
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; RV64I-LABEL: tail_call:
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; RV64I-NOT: call t0, __riscv_save
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; RV64I: tail tail_callee
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; RV64I-NOT: tail __riscv_restore
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;
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; RV32I-SR-LABEL: tail_call:
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; RV32I-SR-NOT: call t0, __riscv_save
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; RV32I-SR: tail tail_callee
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; RV32I-SR-NOT: tail __riscv_restore
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;
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; RV64I-SR-LABEL: tail_call:
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; RV64I-SR-NOT: call t0, __riscv_save
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; RV64I-SR: tail tail_callee
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; RV64I-SR-NOT: tail __riscv_restore
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;
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; RV32I-FP-SR-LABEL: tail_call:
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; RV32I-FP-SR-NOT: call t0, __riscv_save
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; RV32I-FP-SR: tail tail_callee
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; RV32I-FP-SR-NOT: tail __riscv_restore
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;
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; RV64I-FP-SR-LABEL: tail_call:
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; RV64I-FP-SR-NOT: call t0, __riscv_save
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; RV64I-FP-SR: tail tail_callee
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; RV64I-FP-SR-NOT: tail __riscv_restore
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entry:
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%val = load [18 x i32], [18 x i32]* @var0
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store volatile [18 x i32] %val, [18 x i32]* @var0
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%r = tail call i32 @tail_callee(i32 %i)
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ret i32 %r
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}
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; Check that functions with varargs do not use save/restore code
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declare void @llvm.va_start(i8*)
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declare void @llvm.va_end(i8*)
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define i32 @varargs(i8* %fmt, ...) nounwind {
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; RV32I-LABEL: varargs:
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; RV32I-NOT: call t0, __riscv_save
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; RV32I-NOT: tail __riscv_restore
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;
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; RV64I-LABEL: varargs:
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; RV64I-NOT: call t0, __riscv_save
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; RV64I-NOT: tail __riscv_restore
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;
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; RV32I-SR-LABEL: varargs:
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; RV32I-SR-NOT: call t0, __riscv_save
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; RV32I-SR-NOT: tail __riscv_restore
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;
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; RV64I-SR-LABEL: varargs:
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; RV64I-SR-NOT: call t0, __riscv_save
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; RV64I-SR-NOT: tail __riscv_restore
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;
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; RV32I-FP-SR-LABEL: varargs:
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; RV32I-FP-SR-NOT: call t0, __riscv_save
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; RV32I-FP-SR-NOT: tail __riscv_restore
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;
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; RV64I-FP-SR-LABEL: varargs:
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; RV64I-FP-SR-NOT: call t0, __riscv_save
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; RV64I-FP-SR-NOT: tail __riscv_restore
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%va = alloca i8*, align 4
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%1 = bitcast i8** %va to i8*
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call void @llvm.va_start(i8* %1)
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%argp.cur = load i8*, i8** %va, align 4
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%argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
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store i8* %argp.next, i8** %va, align 4
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%2 = bitcast i8* %argp.cur to i32*
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%3 = load i32, i32* %2, align 4
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call void @llvm.va_end(i8* %1)
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ret i32 %3
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}
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define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind {
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; RV32I-LABEL: many_args:
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; RV32I-NOT: call t0, __riscv_save
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; RV32I-NOT: tail __riscv_restore
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;
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; RV64I-LABEL: many_args:
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; RV64I-NOT: call t0, __riscv_save
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; RV64I-NOT: tail __riscv_restore
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;
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; RV32I-SR-LABEL: many_args:
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; RV32I-SR: call t0, __riscv_save_5
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; RV32I-SR: tail __riscv_restore_5
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;
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; RV64I-SR-LABEL: many_args:
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; RV64I-SR: call t0, __riscv_save_5
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; RV64I-SR: tail __riscv_restore_5
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;
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; RV32I-FP-SR-LABEL: many_args:
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; RV32I-FP-SR: call t0, __riscv_save_5
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; RV32I-FP-SR: tail __riscv_restore_5
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;
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; RV64I-FP-SR-LABEL: many_args:
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; RV64I-FP-SR: call t0, __riscv_save_5
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; RV64I-FP-SR: tail __riscv_restore_5
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entry:
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%val = load [18 x i32], [18 x i32]* @var0
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store volatile [18 x i32] %val, [18 x i32]* @var0
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ret void
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}
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; Check that dynamic allocation calculations remain correct
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declare i8* @llvm.stacksave()
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declare void @llvm.stackrestore(i8*)
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declare void @notdead(i8*)
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define void @alloca(i32 %n) nounwind {
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; RV32I-LABEL: alloca:
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; RV32I-NOT: call t0, __riscv_save
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; RV32I: addi s0, sp, 16
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; RV32I: addi sp, s0, -16
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; RV32I-NOT: tail __riscv_restore
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;
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; RV64I-LABEL: alloca:
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; RV64I-NOT: call t0, __riscv_save
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; RV64I: addi s0, sp, 32
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; RV64I: addi sp, s0, -32
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; RV64I-NOT: tail __riscv_restore
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;
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; RV32I-SR-LABEL: alloca:
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; RV32I-SR: call t0, __riscv_save_2
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; RV32I-SR: addi s0, sp, 16
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; RV32I-SR: addi sp, s0, -16
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; RV32I-SR: tail __riscv_restore_2
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;
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; RV64I-SR-LABEL: alloca:
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; RV64I-SR: call t0, __riscv_save_2
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; RV64I-SR: addi s0, sp, 32
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; RV64I-SR: addi sp, s0, -32
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; RV64I-SR: tail __riscv_restore_2
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;
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; RV32I-FP-SR-LABEL: alloca:
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; RV32I-FP-SR: call t0, __riscv_save_2
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; RV32I-FP-SR: addi s0, sp, 16
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; RV32I-FP-SR: addi sp, s0, -16
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; RV32I-FP-SR: tail __riscv_restore_2
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;
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; RV64I-FP-SR-LABEL: alloca:
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; RV64I-FP-SR: call t0, __riscv_save_2
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; RV64I-FP-SR: addi s0, sp, 32
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; RV64I-FP-SR: addi sp, s0, -32
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; RV64I-FP-SR: tail __riscv_restore_2
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%sp = call i8* @llvm.stacksave()
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%addr = alloca i8, i32 %n
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call void @notdead(i8* %addr)
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call void @llvm.stackrestore(i8* %sp)
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ret void
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}
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