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890 lines
18 KiB
890 lines
18 KiB
; Test that compares are omitted if CC already has the right value
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; (z10 version).
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -no-integrated-as \
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; RUN: -verify-machineinstrs| FileCheck %s
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declare void @foo()
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; Addition provides enough for comparisons with zero if we know no
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; signed overflow happens, which is when the "nsw" flag is set.
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; First test the EQ case.
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define i32 @f1(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f1:
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; CHECK: afi %r2, 1000000
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; CHECK-NEXT: ber %r14
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; CHECK: br %r14
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entry:
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%res = add nsw i32 %a, 1000000
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%cmp = icmp eq i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and again with NE.
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define i32 @f2(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f2:
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; CHECK: afi %r2, 1000000
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; CHECK-NEXT: blhr %r14
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; CHECK: br %r14
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entry:
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%res = add nsw i32 %a, 1000000
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%cmp = icmp ne i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and again with SLT.
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define i32 @f3(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f3:
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; CHECK: afi %r2, 1000000
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; CHECK-NEXT: blr %r14
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entry:
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%res = add nsw i32 %a, 1000000
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%cmp = icmp slt i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and again with SLE.
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define i32 @f4(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f4:
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; CHECK: afi %r2, 1000000
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; CHECK-NEXT: bler %r14
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entry:
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%res = add nsw i32 %a, 1000000
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%cmp = icmp sle i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and again with SGT.
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define i32 @f5(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f5:
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; CHECK: afi %r2, 1000000
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; CHECK-NEXT: bhr %r14
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entry:
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%res = add nsw i32 %a, 1000000
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%cmp = icmp sgt i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and again with SGE.
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define i32 @f6(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f6:
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; CHECK: afi %r2, 1000000
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; CHECK-NEXT: bher %r14
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entry:
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%res = add nsw i32 %a, 1000000
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%cmp = icmp sge i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; Subtraction provides in addition also enough for equality comparisons with
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; zero even without "nsw".
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define i32 @f7(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f7:
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; CHECK: s %r2, 0(%r4)
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; CHECK-NEXT: bner %r14
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; CHECK: br %r14
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entry:
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%cur = load i32, i32 *%dest
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%res = sub i32 %a, %cur
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%cmp = icmp ne i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and again with SLT.
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define i32 @f8(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f8:
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; CHECK: s %r2, 0(%r4)
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; CHECK-NEXT: blr %r14
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entry:
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%cur = load i32, i32 *%dest
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%res = sub nsw i32 %a, %cur
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%cmp = icmp slt i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; Logic register-register instructions also provide enough for equality
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; comparisons with zero.
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define i32 @f9(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f9:
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; CHECK: nr %r2, %r3
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; CHECK-NEXT: blr %r14
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; CHECK: br %r14
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entry:
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%res = and i32 %a, %b
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%cmp = icmp ne i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...but not for ordered comparisons.
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define i32 @f10(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f10:
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; CHECK: nr %r2, %r3
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; CHECK-NEXT: cibl %r2, 0, 0(%r14)
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; CHECK: br %r14
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entry:
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%res = and i32 %a, %b
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%cmp = icmp slt i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; Logic register-immediate instructions also provide enough for equality
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; comparisons with zero if the immediate covers the whole register.
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define i32 @f11(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f11:
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; CHECK: nilf %r2, 100000001
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; CHECK-NEXT: blr %r14
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; CHECK: br %r14
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entry:
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%res = and i32 %a, 100000001
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%cmp = icmp ne i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; Partial logic register-immediate instructions do not provide simple
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; zero results.
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define i32 @f12(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f12:
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; CHECK: nill %r2, 65436
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; CHECK-NEXT: ciblh %r2, 0, 0(%r14)
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; CHECK: br %r14
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entry:
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%res = and i32 %a, -100
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%cmp = icmp ne i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; SRA provides the same CC result as a comparison with zero.
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define i32 @f13(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f13:
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; CHECK: sra %r2, 0(%r3)
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; CHECK-NEXT: ber %r14
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; CHECK: br %r14
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entry:
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%res = ashr i32 %a, %b
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%cmp = icmp eq i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and again with NE.
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define i32 @f14(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f14:
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; CHECK: sra %r2, 0(%r3)
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; CHECK-NEXT: blhr %r14
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; CHECK: br %r14
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entry:
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%res = ashr i32 %a, %b
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%cmp = icmp ne i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and SLT.
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define i32 @f15(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f15:
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; CHECK: sra %r2, 0(%r3)
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; CHECK-NEXT: blr %r14
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; CHECK: br %r14
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entry:
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%res = ashr i32 %a, %b
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%cmp = icmp slt i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and SLE.
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define i32 @f16(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f16:
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; CHECK: sra %r2, 0(%r3)
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; CHECK-NEXT: bler %r14
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; CHECK: br %r14
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entry:
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%res = ashr i32 %a, %b
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%cmp = icmp sle i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and SGT.
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define i32 @f17(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f17:
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; CHECK: sra %r2, 0(%r3)
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; CHECK-NEXT: bhr %r14
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; CHECK: br %r14
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entry:
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%res = ashr i32 %a, %b
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%cmp = icmp sgt i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and SGE.
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define i32 @f18(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f18:
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; CHECK: sra %r2, 0(%r3)
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; CHECK-NEXT: bher %r14
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; CHECK: br %r14
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entry:
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%res = ashr i32 %a, %b
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%cmp = icmp sge i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; RISBG provides the same result as a comparison against zero.
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; Test the EQ case.
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define i64 @f19(i64 %a, i64 %b, i64 *%dest) {
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; CHECK-LABEL: f19:
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; CHECK: risbg %r2, %r3, 0, 190, 0
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; CHECK-NEXT: ber %r14
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; CHECK: br %r14
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entry:
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%res = and i64 %b, -2
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%cmp = icmp eq i64 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i64 %b, i64 *%dest
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br label %exit
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exit:
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ret i64 %res
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}
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; ...and the SLT case.
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define i64 @f20(i64 %a, i64 %b, i64 *%dest) {
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; CHECK-LABEL: f20:
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; CHECK: risbg %r2, %r3, 0, 190, 0
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; CHECK-NEXT: blr %r14
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; CHECK: br %r14
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entry:
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%res = and i64 %b, -2
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%cmp = icmp slt i64 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i64 %b, i64 *%dest
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br label %exit
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exit:
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ret i64 %res
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}
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|
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; Test a case where the register we're testing is set by a non-CC-clobbering
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; instruction.
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define i32 @f21(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f21:
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; CHECK: afi %r2, 1000000
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; CHECK-NEXT: #APP
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; CHECK-NEXT: blah %r2
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: cibe %r2, 0, 0(%r14)
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; CHECK: br %r14
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entry:
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%add = add i32 %a, 1000000
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%res = call i32 asm "blah $0", "=r,0" (i32 %add)
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%cmp = icmp eq i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and again with a CC-clobbering instruction.
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define i32 @f22(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f22:
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|
; CHECK: afi %r2, 1000000
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|
; CHECK-NEXT: #APP
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|
; CHECK-NEXT: blah %r2
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; CHECK-NEXT: #NO_APP
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|
; CHECK-NEXT: cibe %r2, 0, 0(%r14)
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; CHECK: br %r14
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|
entry:
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|
%add = add i32 %a, 1000000
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|
%res = call i32 asm "blah $0", "=r,0,~{cc}" (i32 %add)
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%cmp = icmp eq i32 %res, 0
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br i1 %cmp, label %exit, label %store
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|
store:
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|
store i32 %b, i32 *%dest
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|
br label %exit
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|
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|
exit:
|
|
ret i32 %res
|
|
}
|
|
|
|
; Check that stores do not interfere.
|
|
define i32 @f23(i32 %a, i32 %b, i32 *%dest1, i32 *%dest2) {
|
|
; CHECK-LABEL: f23:
|
|
; CHECK: afi %r2, 1000000
|
|
; CHECK-NEXT: st %r2, 0(%r4)
|
|
; CHECK-NEXT: blhr %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
%res = add nsw i32 %a, 1000000
|
|
store i32 %res, i32 *%dest1
|
|
%cmp = icmp ne i32 %res, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i32 %b, i32 *%dest2
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i32 %res
|
|
}
|
|
|
|
; Check that calls do interfere.
|
|
define void @f24(i32 *%ptr) {
|
|
; CHECK-LABEL: f24:
|
|
; CHECK: afi [[REG:%r[0-9]+]], 1000000
|
|
; CHECK-NEXT: brasl %r14, foo@PLT
|
|
; CHECK-NEXT: cijlh [[REG]], 0, .L{{.*}}
|
|
; CHECK: br %r14
|
|
entry:
|
|
%val = load i32, i32 *%ptr
|
|
%xor = xor i32 %val, 1
|
|
%add = add i32 %xor, 1000000
|
|
call void @foo()
|
|
%cmp = icmp eq i32 %add, 0
|
|
br i1 %cmp, label %store, label %exit, !prof !1
|
|
|
|
store:
|
|
store i32 %add, i32 *%ptr
|
|
br label %exit
|
|
|
|
exit:
|
|
ret void
|
|
}
|
|
|
|
; Check that inline asms don't interfere if they don't clobber CC.
|
|
define void @f25(i32 %a, i32 *%ptr) {
|
|
; CHECK-LABEL: f25:
|
|
; CHECK: afi %r2, 1000000
|
|
; CHECK-NEXT: #APP
|
|
; CHECK-NEXT: blah
|
|
; CHECK-NEXT: #NO_APP
|
|
; CHECK-NEXT: blhr %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
%add = add nsw i32 %a, 1000000
|
|
call void asm sideeffect "blah", "r"(i32 %add)
|
|
%cmp = icmp ne i32 %add, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i32 %add, i32 *%ptr
|
|
br label %exit
|
|
|
|
exit:
|
|
ret void
|
|
}
|
|
|
|
; ...but do interfere if they do clobber CC.
|
|
define void @f26(i32 %a, i32 *%ptr) {
|
|
; CHECK-LABEL: f26:
|
|
; CHECK: afi %r2, 1000000
|
|
; CHECK-NEXT: #APP
|
|
; CHECK-NEXT: blah
|
|
; CHECK-NEXT: #NO_APP
|
|
; CHECK-NEXT: ciblh %r2, 0, 0(%r14)
|
|
; CHECK: br %r14
|
|
entry:
|
|
%add = add i32 %a, 1000000
|
|
call void asm sideeffect "blah", "r,~{cc}"(i32 %add)
|
|
%cmp = icmp ne i32 %add, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i32 %add, i32 *%ptr
|
|
br label %exit
|
|
|
|
exit:
|
|
ret void
|
|
}
|
|
|
|
; Test a case where CC is set based on a different register from the
|
|
; compare input.
|
|
define i32 @f27(i32 %a, i32 %b, i32 *%dest1, i32 *%dest2) {
|
|
; CHECK-LABEL: f27:
|
|
; CHECK: afi %r2, 1000000
|
|
; CHECK-NEXT: sr %r3, %r2
|
|
; CHECK-NEXT: st %r3, 0(%r4)
|
|
; CHECK-NEXT: cibe %r2, 0, 0(%r14)
|
|
; CHECK: br %r14
|
|
entry:
|
|
%add = add nsw i32 %a, 1000000
|
|
%sub = sub i32 %b, %add
|
|
store i32 %sub, i32 *%dest1
|
|
%cmp = icmp eq i32 %add, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i32 %sub, i32 *%dest2
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i32 %add
|
|
}
|
|
|
|
; Make sure that we don't confuse a base register for a destination.
|
|
define void @f28(i64 %a, i64 *%dest) {
|
|
; CHECK-LABEL: f28:
|
|
; CHECK: xi 0(%r2), 15
|
|
; CHECK: cgibe %r2, 0, 0(%r14)
|
|
; CHECK: br %r14
|
|
entry:
|
|
%ptr = inttoptr i64 %a to i8 *
|
|
%val = load i8, i8 *%ptr
|
|
%xor = xor i8 %val, 15
|
|
store i8 %xor, i8 *%ptr
|
|
%cmp = icmp eq i64 %a, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i64 %a, i64 *%dest
|
|
br label %exit
|
|
|
|
exit:
|
|
ret void
|
|
}
|
|
|
|
; Test that L gets converted to LT where useful.
|
|
define i32 @f29(i64 %base, i64 %index, i32 *%dest) {
|
|
; CHECK-LABEL: f29:
|
|
; CHECK: lt %r2, 0({{%r2,%r3|%r3,%r2}})
|
|
; CHECK-NEXT: bler %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
%add = add i64 %base, %index
|
|
%ptr = inttoptr i64 %add to i32 *
|
|
%res = load i32, i32 *%ptr
|
|
%cmp = icmp sle i32 %res, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i32 %res, i32 *%dest
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i32 %res
|
|
}
|
|
|
|
; Test that LY gets converted to LT where useful.
|
|
define i32 @f30(i64 %base, i64 %index, i32 *%dest) {
|
|
; CHECK-LABEL: f30:
|
|
; CHECK: lt %r2, 100000({{%r2,%r3|%r3,%r2}})
|
|
; CHECK-NEXT: bler %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
%add1 = add i64 %base, %index
|
|
%add2 = add i64 %add1, 100000
|
|
%ptr = inttoptr i64 %add2 to i32 *
|
|
%res = load i32, i32 *%ptr
|
|
%cmp = icmp sle i32 %res, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i32 %res, i32 *%dest
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i32 %res
|
|
}
|
|
|
|
; Test that LG gets converted to LTG where useful.
|
|
define i64 @f31(i64 %base, i64 %index, i64 *%dest) {
|
|
; CHECK-LABEL: f31:
|
|
; CHECK: ltg %r2, 0({{%r2,%r3|%r3,%r2}})
|
|
; CHECK-NEXT: bher %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
%add = add i64 %base, %index
|
|
%ptr = inttoptr i64 %add to i64 *
|
|
%res = load i64, i64 *%ptr
|
|
%cmp = icmp sge i64 %res, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i64 %res, i64 *%dest
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i64 %res
|
|
}
|
|
|
|
; Test that LGF gets converted to LTGF where useful.
|
|
define i64 @f32(i64 %base, i64 %index, i64 *%dest) {
|
|
; CHECK-LABEL: f32:
|
|
; CHECK: ltgf %r2, 0({{%r2,%r3|%r3,%r2}})
|
|
; CHECK-NEXT: bhr %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
%add = add i64 %base, %index
|
|
%ptr = inttoptr i64 %add to i32 *
|
|
%val = load i32, i32 *%ptr
|
|
%res = sext i32 %val to i64
|
|
%cmp = icmp sgt i64 %res, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i64 %res, i64 *%dest
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i64 %res
|
|
}
|
|
|
|
; Test that LR gets converted to LTR where useful.
|
|
define i32 @f33(i32 %dummy, i32 %val, i32 *%dest) {
|
|
; CHECK-LABEL: f33:
|
|
; CHECK: ltr %r2, %r3
|
|
; CHECK-NEXT: #APP
|
|
; CHECK-NEXT: blah %r2
|
|
; CHECK-NEXT: #NO_APP
|
|
; CHECK-NEXT: blr %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
call void asm sideeffect "blah $0", "{r2}"(i32 %val)
|
|
%cmp = icmp slt i32 %val, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i32 %val, i32 *%dest
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i32 %val
|
|
}
|
|
|
|
; Test that LGR gets converted to LTGR where useful.
|
|
define i64 @f34(i64 %dummy, i64 %val, i64 *%dest) {
|
|
; CHECK-LABEL: f34:
|
|
; CHECK: ltgr %r2, %r3
|
|
; CHECK-NEXT: #APP
|
|
; CHECK-NEXT: blah %r2
|
|
; CHECK-NEXT: #NO_APP
|
|
; CHECK-NEXT: bhr %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
call void asm sideeffect "blah $0", "{r2}"(i64 %val)
|
|
%cmp = icmp sgt i64 %val, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i64 %val, i64 *%dest
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i64 %val
|
|
}
|
|
|
|
; Test that LGFR gets converted to LTGFR where useful.
|
|
define i64 @f35(i64 %dummy, i32 %val, i64 *%dest) {
|
|
; CHECK-LABEL: f35:
|
|
; CHECK: ltgfr %r2, %r3
|
|
; CHECK-NEXT: #APP
|
|
; CHECK-NEXT: blah %r2
|
|
; CHECK-NEXT: #NO_APP
|
|
; CHECK-NEXT: bhr %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
%ext = sext i32 %val to i64
|
|
call void asm sideeffect "blah $0", "{r2}"(i64 %ext)
|
|
%cmp = icmp sgt i64 %ext, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i64 %ext, i64 *%dest
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i64 %ext
|
|
}
|
|
|
|
; Test a case where it is the source rather than destination of LR that
|
|
; we need.
|
|
define i32 @f36(i32 %val, i32 %dummy, i32 *%dest) {
|
|
; CHECK-LABEL: f36:
|
|
; CHECK: ltr %r3, %r2
|
|
; CHECK-NEXT: #APP
|
|
; CHECK-NEXT: blah %r3
|
|
; CHECK-NEXT: #NO_APP
|
|
; CHECK-NEXT: blr %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
call void asm sideeffect "blah $0", "{r3}"(i32 %val)
|
|
%cmp = icmp slt i32 %val, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i32 %val, i32 *%dest
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i32 %val
|
|
}
|
|
|
|
; Test a case where it is the source rather than destination of LGR that
|
|
; we need.
|
|
define i64 @f37(i64 %val, i64 %dummy, i64 *%dest) {
|
|
; CHECK-LABEL: f37:
|
|
; CHECK: ltgr %r3, %r2
|
|
; CHECK-NEXT: #APP
|
|
; CHECK-NEXT: blah %r3
|
|
; CHECK-NEXT: #NO_APP
|
|
; CHECK-NEXT: blr %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
call void asm sideeffect "blah $0", "{r3}"(i64 %val)
|
|
%cmp = icmp slt i64 %val, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i64 %val, i64 *%dest
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i64 %val
|
|
}
|
|
|
|
; Test a case where it is the source rather than destination of LGFR that
|
|
; we need.
|
|
define i32 @f38(i32 %val, i64 %dummy, i32 *%dest) {
|
|
; CHECK-LABEL: f38:
|
|
; CHECK: ltgfr %r3, %r2
|
|
; CHECK-NEXT: #APP
|
|
; CHECK-NEXT: blah %r3
|
|
; CHECK-NEXT: #NO_APP
|
|
; CHECK-NEXT: blr %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
%ext = sext i32 %val to i64
|
|
call void asm sideeffect "blah $0", "{r3}"(i64 %ext)
|
|
%cmp = icmp slt i32 %val, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i32 %val, i32 *%dest
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i32 %val
|
|
}
|
|
|
|
; Test f35 for in-register extensions.
|
|
define i64 @f39(i64 %dummy, i64 %a, i64 *%dest) {
|
|
; CHECK-LABEL: f39:
|
|
; CHECK: ltgfr %r2, %r3
|
|
; CHECK-NEXT: #APP
|
|
; CHECK-NEXT: blah %r2
|
|
; CHECK-NEXT: #NO_APP
|
|
; CHECK-NEXT: bhr %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
%val = trunc i64 %a to i32
|
|
%ext = sext i32 %val to i64
|
|
call void asm sideeffect "blah $0", "{r2}"(i64 %ext)
|
|
%cmp = icmp sgt i64 %ext, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i64 %ext, i64 *%dest
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i64 %ext
|
|
}
|
|
|
|
; ...and again with what InstCombine would produce for f40.
|
|
define i64 @f40(i64 %dummy, i64 %a, i64 *%dest) {
|
|
; CHECK-LABEL: f40:
|
|
; CHECK: ltgfr %r2, %r3
|
|
; CHECK-NEXT: #APP
|
|
; CHECK-NEXT: blah %r2
|
|
; CHECK-NEXT: #NO_APP
|
|
; CHECK-NEXT: bhr %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
%shl = shl i64 %a, 32
|
|
%ext = ashr i64 %shl, 32
|
|
call void asm sideeffect "blah $0", "{r2}"(i64 %ext)
|
|
%cmp = icmp sgt i64 %shl, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i64 %ext, i64 *%dest
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i64 %ext
|
|
}
|
|
|
|
; Try a form of f7 in which the subtraction operands are compared directly.
|
|
define i32 @f41(i32 %a, i32 %b, i32 *%dest) {
|
|
; CHECK-LABEL: f41:
|
|
; CHECK: s %r2, 0(%r4)
|
|
; CHECK-NEXT: bner %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
%cur = load i32, i32 *%dest
|
|
%res = sub i32 %a, %cur
|
|
%cmp = icmp ne i32 %a, %cur
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i32 %b, i32 *%dest
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i32 %res
|
|
}
|
|
|
|
; A version of f32 that tests the unextended value.
|
|
define i64 @f42(i64 %base, i64 %index, i64 *%dest) {
|
|
; CHECK-LABEL: f42:
|
|
; CHECK: ltgf %r2, 0({{%r2,%r3|%r3,%r2}})
|
|
; CHECK-NEXT: bhr %r14
|
|
; CHECK: br %r14
|
|
entry:
|
|
%add = add i64 %base, %index
|
|
%ptr = inttoptr i64 %add to i32 *
|
|
%val = load i32, i32 *%ptr
|
|
%res = sext i32 %val to i64
|
|
%cmp = icmp sgt i32 %val, 0
|
|
br i1 %cmp, label %exit, label %store
|
|
|
|
store:
|
|
store i64 %res, i64 *%dest
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i64 %res
|
|
}
|
|
|
|
!1 = !{!"branch_weights", i32 2, i32 1}
|